Author: wmb Date: Thu Aug 23 22:13:41 2012 New Revision: 3214 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3214
Log: OLPC ARM - /apbc node had incorrect enable values.
Modified: cpu/arm/mmp2/apbc.fth
Modified: cpu/arm/mmp2/apbc.fth ============================================================================== --- cpu/arm/mmp2/apbc.fth Thu Aug 23 22:12:25 2012 (r3213) +++ cpu/arm/mmp2/apbc.fth Thu Aug 23 22:13:41 2012 (r3214) @@ -51,42 +51,42 @@
0 0 encode-bytes \ offset clr-mask value rate -h# 00 +int h# f7 +int h# 87 +int d# 32,768 +int \ 00 RTC -h# 04 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 01 TWSI1 -h# 08 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 02 TWSI2 -h# 0c +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 03 TWSI3 -h# 10 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 04 TWSI4 -h# 14 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 05 ONEWIRE -h# 18 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 06 KPC -h# 1c +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 07 TB_ROTARY -h# 20 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 08 SW_JTAG -h# 24 +int h# 77 +int h# 17 +int d# 6,500,000 +int \ 09 TIMERS1 -h# 2c +int h# 77 +int h# 17 +int d# 26,000,000 +int \ 10 UART1 -h# 30 +int h# 77 +int h# 17 +int d# 26,000,000 +int \ 11 UART2 -h# 34 +int h# 77 +int h# 17 +int d# 26,000,000 +int \ 12 UART3 -h# 38 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 13 GPIO -h# 3c +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 14 PWM0 -h# 40 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 15 PWM1 -h# 44 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 16 PWM2 -h# 48 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 17 PWM3 -h# 4c +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 18 SSP0 -h# 50 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 19 SSP1 -h# 54 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 20 SSP2 -h# 58 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 21 SSP3 -h# 5c +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 22 SSP4 -h# 60 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 23 SSP5 -h# 64 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 24 AIB -h# 68 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 25 ASFAR -h# 6c +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 26 ASSAR -h# 70 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 27 USIM -h# 74 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 28 MPMU -h# 78 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 29 IPC -h# 7c +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 30 TWSI5 -h# 80 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 31 TWSI6 -h# 88 +int h# 77 +int h# 17 +int d# 26,000,000 +int \ 32 UART4 -h# 8c +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 33 RIPC -h# 90 +int h# 77 +int h# 7 +int d# 26,000,000 +int \ 34 THSENS1 -h# 94 +int h# 7 +int h# 7 +int d# 26,000,000 +int \ 35 CORESIGHT +h# 00 +int h# f7 +int h# 83 +int d# 32,768 +int \ 00 RTC +h# 04 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 01 TWSI1 +h# 08 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 02 TWSI2 +h# 0c +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 03 TWSI3 +h# 10 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 04 TWSI4 +h# 14 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 05 ONEWIRE +h# 18 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 06 KPC +h# 1c +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 07 TB_ROTARY +h# 20 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 08 SW_JTAG +h# 24 +int h# 77 +int h# 13 +int d# 6,500,000 +int \ 09 TIMERS1 +h# 2c +int h# 77 +int h# 13 +int d# 26,000,000 +int \ 10 UART1 +h# 30 +int h# 77 +int h# 13 +int d# 26,000,000 +int \ 11 UART2 +h# 34 +int h# 77 +int h# 13 +int d# 26,000,000 +int \ 12 UART3 +h# 38 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 13 GPIO +h# 3c +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 14 PWM0 +h# 40 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 15 PWM1 +h# 44 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 16 PWM2 +h# 48 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 17 PWM3 +h# 4c +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 18 SSP0 +h# 50 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 19 SSP1 +h# 54 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 20 SSP2 +h# 58 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 21 SSP3 +h# 5c +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 22 SSP4 +h# 60 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 23 SSP5 +h# 64 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 24 AIB +h# 68 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 25 ASFAR +h# 6c +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 26 ASSAR +h# 70 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 27 USIM +h# 74 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 28 MPMU +h# 78 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 29 IPC +h# 7c +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 30 TWSI5 +h# 80 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 31 TWSI6 +h# 88 +int h# 77 +int h# 13 +int d# 26,000,000 +int \ 32 UART4 +h# 8c +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 33 RIPC +h# 90 +int h# 77 +int h# 3 +int d# 26,000,000 +int \ 34 THSENS1 +h# 94 +int h# 7 +int h# 3 +int d# 26,000,000 +int \ 35 CORESIGHT " clock-enable-registers" property
end-package