Author: wmb Date: 2009-11-21 04:40:50 +0100 (Sat, 21 Nov 2009) New Revision: 1496
Modified: cpu/x86/pc/olpc/via/demodram.fth cpu/x86/pc/olpc/via/dramtiming.fth cpu/x86/pc/olpc/via/startdraminit.fth Log: OLPC trac 9727 - Made the DRAM CAS latency setting dependent on memory ID0 strapping, to support new DRAM chips that require CL=4.
Modified: cpu/x86/pc/olpc/via/demodram.fth =================================================================== --- cpu/x86/pc/olpc/via/demodram.fth 2009-11-21 03:38:43 UTC (rev 1495) +++ cpu/x86/pc/olpc/via/demodram.fth 2009-11-21 03:40:50 UTC (rev 1496) @@ -53,7 +53,6 @@
\ 61 ff 12 mreg \ Trfc, Trrd Trfc = 0x39+8 = 65 Trrd=4T ceil(7.5ns/5ns)
- 62 07 TCL 2 - mreg \ CL 3 62 08 08 mreg \ 8-bank timing constraint \ !!! 62 f0 Tras ns>tck 5 - 4 << mreg \ Tras: ceil( 40.00/5) = 8 - 5 = 0x03 @@ -77,6 +76,17 @@ [then] end-table
+ acpi-io-base 48 + port-rl h# 0008.0000 # ax and 0<> if \ Memory ID0 bit - set for CL4 SDRAM + 0 3 devfunc + 62 07 4 2 - mreg \ CL 4 + end-table + else + 0 3 devfunc + 62 07 3 2 - mreg \ CL 3 + end-table + then + + \ DRAMBurstLength 0 3 devfunc 6c 08 08 mreg \ Burst length 8
Modified: cpu/x86/pc/olpc/via/dramtiming.fth =================================================================== --- cpu/x86/pc/olpc/via/dramtiming.fth 2009-11-21 03:38:43 UTC (rev 1495) +++ cpu/x86/pc/olpc/via/dramtiming.fth 2009-11-21 03:40:50 UTC (rev 1496) @@ -36,7 +36,9 @@ d# 125.00 constant Trfc \ Fudged to get same setting as Phoenix d# 7.50 constant Trrd \ d# 10.00 constant Trrd -d# 3 constant TCL +\ TCL depends on the type of RAM chip, so it is set dynamically +\ d# 3 constant TCL \ Normal value +\ d# 4 constant TCL \ For new RAM chips \ d# 40.00 constant Tras d# 45.00 constant Tras d# 15.00 constant Twr @@ -95,3 +97,15 @@ ;
: dblfudge32 2/ ; + +0 [if] +: mrs-value ( -- n ) + 3 \ code for burst length 8; use 2 for burst length 4 + 1 3 lshift or \ Interleaved bursts + TCL 4 lshift or \ CAS Latency + 0 7 lshift or \ Normal mode, not test mode + 0 8 lshift or \ Not DLL reset + Twr Tck / 1- scramble-mrs or \ Twr cycles minus 1 + 3 lshift +; +[then]
Modified: cpu/x86/pc/olpc/via/startdraminit.fth =================================================================== --- cpu/x86/pc/olpc/via/startdraminit.fth 2009-11-21 03:38:43 UTC (rev 1495) +++ cpu/x86/pc/olpc/via/startdraminit.fth 2009-11-21 03:40:50 UTC (rev 1496) @@ -24,8 +24,13 @@
13 36b config-wb \ SDRAM MRS Enable \ 101258 #) ax mov \ Depends on Twr, CL, and Burst Length - 1021d8 #) ax mov \ Depends on Twr, CL, and Burst Length
+ acpi-io-base 48 + port-rl h# 0008.0000 # ax and 0<> if \ Memory ID0 bit - set for CL4 SDRAM + 102258 #) ax mov \ Depends on Twr, CL, and Burst Length - CL4 + else + 1021d8 #) ax mov \ Depends on Twr, CL, and Burst Length - CL3 + then + 0 [if] 2024b 011 BL 8