Author: wmb Date: Fri Aug 3 08:56:17 2012 New Revision: 3121 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3121
Log: OLPC CL4 - Fix the USB PLL frequency.
Modified: cpu/arm/mmp3/usb2phy.fth
Modified: cpu/arm/mmp3/usb2phy.fth ============================================================================== --- cpu/arm/mmp3/usb2phy.fth Fri Aug 3 08:06:11 2012 (r3120) +++ cpu/arm/mmp3/usb2phy.fth Fri Aug 3 08:56:17 2012 (r3121) @@ -41,10 +41,8 @@ \ h# d00 h# 100 +pmua io-set \ Select 26 MHz VCXO clock h# 000 h# 100 +pmua io-set \ Select crystal
-\ h# 3fff pll-reg0 io-clr \ REFDIV_MASK_B0 3e00, FBDIV_MASK_B0 01ff -\ h# 1af0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 \ h# ca60 is the value to use for a 25 MHz crystal - h# daf0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 + h# daf0 pll-reg0 io! \ REFDIV: 0xd << 9, FBDIV: 0xf0 << 0
h# 3000 reserve-reg0 io! \ Program PLLVDD12 per Marvell email