Author: wmb Date: Wed Aug 1 10:26:00 2012 New Revision: 3112 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3112
Log: OLPC CL4 - Use different value for LCD clock divisor because the clock source select field moved.
Modified: cpu/arm/olpc/lcd.fth
Modified: cpu/arm/olpc/lcd.fth ============================================================================== --- cpu/arm/olpc/lcd.fth Wed Aug 1 10:23:34 2012 (r3111) +++ cpu/arm/olpc/lcd.fth Wed Aug 1 10:26:00 2012 (r3112) @@ -8,7 +8,15 @@ " /pmua" encode-phandle 1 encode-int encode+ " clocks" property d# 41 " interrupts" integer-property
+[ifdef] olpc-cl4 +\ This value has the same effect as the value below. The +\ difference is that the SCLK_SOURCE_SELECT field added a +\ low-order bit (bit 29), so the high nibble changed from +\ 2 to 4 even though the field value is still 1. +h# 20001102 value clkdiv \ Display Clock 1 / 2 -> 56.93 MHz +[else] h# 40001102 value clkdiv \ Display Clock 1 / 2 -> 56.93 MHz +[then] h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz
d# 8 value hsync \ Sync width