Author: wmb Date: 2009-10-12 21:50:49 +0200 (Mon, 12 Oct 2009) New Revision: 1419
Modified: cpu/x86/pc/olpc/via/romreset.bth Log: Via - Moved the enabling of power-glitch suppression to happen after other register initialization, thus preventing write-lockout of some power well registers.
Modified: cpu/x86/pc/olpc/via/romreset.bth =================================================================== --- cpu/x86/pc/olpc/via/romreset.bth 2009-10-12 07:51:36 UTC (rev 1418) +++ cpu/x86/pc/olpc/via/romreset.bth 2009-10-12 19:50:49 UTC (rev 1419) @@ -125,8 +125,6 @@ cominit #) call [then]
- 8c 8881 config-wb \ Enable ACPI regs, 32-bit PM timer, guard RTC against power glitches - char + report long-offsets on
@@ -215,6 +213,9 @@ fload ${BP}/cpu/x86/pc/olpc/via/starttherm.fth \ Enables thermal monitor fload ${BP}/cpu/x86/pc/olpc/via/startcpuspeed.fth \ Turns up clock rate
+ \ Do this as late as possible so power well registers aren't locked out by the glitch suppressor + 8c 8881 config-wb \ Enable ACPI regs, 32-bit PM timer, guard RTC against power glitches + \ Cache is now setup normally, backed by memory \ Setup a small stack for subroutine calls h# 10.0000 # esp mov