Author: wmb Date: 2009-09-05 11:07:41 +0200 (Sat, 05 Sep 2009) New Revision: 1350
Modified: cpu/x86/pc/olpc/via/romreset.bth cpu/x86/pc/olpc/via/startcacheasram.fth Log: Via - speed up startup by eliminating unnecessary cache prefill from slow ROM, but add back just the right amount of explicit delay to ensure that the system starts properly.
Modified: cpu/x86/pc/olpc/via/romreset.bth =================================================================== --- cpu/x86/pc/olpc/via/romreset.bth 2009-09-05 09:05:43 UTC (rev 1349) +++ cpu/x86/pc/olpc/via/romreset.bth 2009-09-05 09:07:41 UTC (rev 1350) @@ -92,7 +92,7 @@
fload ${BP}/cpu/x86/pc/olpc/via/startcacheasram.fth
- \ We are now running from cache and can use the stack + d# 40000 wait-us \ This delay is empirically necessary - minimum is 36000 - about 50 ms
\ cache_as_ram_auto.c: amd64_main()
@@ -131,7 +131,7 @@ \ This turns an OS reboot into a real cold start - from coreboot h# 380 config-rb ax ax or 0<> if \ C-page shadowing not on yet 6 h# cf9 port-wb \ Force a full system reset - char X report + char X report begin hlt again then char F report @@ -169,6 +169,7 @@ fload ${BP}/cpu/x86/pc/olpc/via/startmtrrinit.fth
fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth +\ XXX need to move startcpuspeed to here
acpi-io-base 4 + port-rw \ Get APCI Status register ax bx mov
Modified: cpu/x86/pc/olpc/via/startcacheasram.fth =================================================================== --- cpu/x86/pc/olpc/via/startcacheasram.fth 2009-09-05 09:05:43 UTC (rev 1349) +++ cpu/x86/pc/olpc/via/startcacheasram.fth 2009-09-05 09:07:41 UTC (rev 1350) @@ -26,16 +26,6 @@
cld
- \ Access ROM to load it into the icache - dropin-base # esi mov - /icached 4 / # ecx mov - rep eax lods - - \ Access "RAM" area to load it into the dcache - dcached-base # esi mov - /dcached 4 / # ecx mov - rep eax lods - \ Put the stack pointer at the top of the dcached area dcached-base /dcached + 4 - # esp mov ds ax mov ax ss mov