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[commit] r2353 - clients/lib
by repository service 14 Jul '11

14 Jul '11

Author: quozl Date: Thu Jul 14 04:05:00 2011 New Revision: 2353 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2353 Log: memcmp version from multicast-nand moved into library, Mitch identified it as better than the one that was there. Modified: clients/lib/mem.c Modified: clients/lib/mem.c ============================================================================== --- clients/lib/mem.c Thu Jul 14 01:28:41 2011 (r2352) +++ clients/lib/mem.c Thu Jul 14 04:05:00 2011 (r2353) @@ -17,10 +17,13 @@ } int -memcmp(void *s1, void *s2, int len) +memcmp(const void *s1, const void *s2, size_t n) { - for (; len--; ++s1, ++s2) - if (*(unsigned char *)s1 != *(unsigned char *)s2) - return *(unsigned char *)s1 - *(unsigned char *)s2; + int diff; + while (n--) { + diff = *(unsigned char *)s1++ - *(unsigned char *)s2++; + if (diff) + return (diff < 0) ? -1 : 1; + } return 0; }

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[commit] r2352 - cpu/arm/olpc/1.75
by repository service 14 Jul '11

14 Jul '11

Author: wmb Date: Thu Jul 14 01:28:41 2011 New Revision: 2352 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2352 Log: OLPC XO-1.75 - fixed DRAM timings to match Marvell's latest recommendations. This is in the version of the file that splits out the parameters into individual fields, not the digested version that is used in CForth for the actual parameter setting. Modified: cpu/arm/olpc/1.75/xo-dram.fth Modified: cpu/arm/olpc/1.75/xo-dram.fth ============================================================================== --- cpu/arm/olpc/1.75/xo-dram.fth Thu Jul 14 01:12:07 2011 (r2351) +++ cpu/arm/olpc/1.75/xo-dram.fth Thu Jul 14 01:28:41 2011 (r2352) @@ -77,16 +77,16 @@ mmap0 h# 0000.0000 d# 23 rshift start-addr -h# 4000.0000 log2 d# 16 - area-length +h# 2000.0000 log2 d# 16 - area-length h# 0000.0000 d# 23 rshift addr-mask 1 cs-valid outbits mmap1 -h# 4000.0000 d# 23 rshift start-addr -h# 4000.0000 log2 d# 16 - area-length +h# 2000.0000 d# 23 rshift start-addr +h# 2000.0000 log2 d# 16 - area-length h# 0000.0000 d# 23 rshift addr-mask -0 cs-valid +1 cs-valid outbits sdram-config-type1-cs0 @@ -166,16 +166,16 @@ outbits sdram-timing4 -d# 5.625 ns>clk d# 4 max tcke +d# 5.625 ns>clk ( d# 4 max ) tcke d# 200000.000 ns>clk d# 1024 /roundup init-count - 1 trwd-ext-dly + 2 trwd-ext-dly d# 100.000 ns>clk reset-count -d# 390 init-count-nop +d# 391 init-count-nop outbits sdram-timing5 d# 37.500 ns>clk 0 max tras -d# 37.500 ns>clk 0 max tfaw +d# 37.500 ns>clk d# 20 max tfaw d# 1 tccd-ccs-ext-dly outbits @@ -186,9 +186,9 @@ outbits sdram-ctrl1 -1 aps-en -1 aps-type -4 aps-value +0 aps-en \ 1 aps-en +0 aps-type \ 1 aps-type +0 aps-value \ 4 aps-value d# 12.500 ns>clk acs-exit-dly 0 acs-en 0 dll-reset @@ -198,14 +198,14 @@ outbits sdram-ctrl2 -0 ref-posted-en -0 ref-posted-max -d# 16 sdram-line-boundary +1 ref-posted-en +7 ref-posted-max +d# 8 sdram-line-boundary 0 refpb-mode 0 pd-mode 0 2t-mode 0 rdimm-mode -1 aprecharge +0 aprecharge 0 int-shadow-mode 0 test-mode outbits @@ -235,9 +235,9 @@ 0 al-number \ unsupported 0 al-en 0 rq-ds-en -3 cas-latency \ For DDR3, upper 3 bits of CL - so 3 for CL6 and CL7 +2 cas-latency \ For DDR3, upper 3 bits of CL - so 3 for CL6 and CL7 0 cas-latency-lower \ For DDR3, lower bit of CL - so 0 for CL6, 1 for CL7 -1 cwl \ 0 for WL5, 1 for WL6, 2 for WL7, 3 for WL8 +0 cwl \ 0 for WL5, 1 for WL6, 2 for WL7, 3 for WL8 0 s4-type \ LPDDR2 only 0 asr \ DDR3 only 0 srt \ DDR3 only @@ -267,7 +267,7 @@ outbits sdram-ctrl8-odt-ctrl2 -1 xpage-en +0 xpage-en 3 mc-queue-size-f 3 mc-queue-size outbits @@ -354,37 +354,11 @@ 0 write-protection outbits -phy-ctrl11 -0 mc-sync-type -outbits - -\ This is the base value -phy-ctrl14 -1 phy-sync-en -0 dll-update-en -0 phy-dll-rst -0 phy-pll-rst -0 dll-update-en-static -outbits - -\ Assert DLL reset -phy-ctrl14 -1 phy-sync-en -0 dll-update-en -1 phy-dll-rst -0 phy-pll-rst -0 dll-update-en-static -outbits - -\ Release DLL reset -phy-ctrl14 -1 phy-sync-en -0 dll-update-en -0 phy-dll-rst -0 phy-pll-rst -0 dll-update-en-static -outbits +\ phy-ctrl11 +\ 0 mc-sync-type +\ outbits +0 [if] \ First value, with auto-cal enabled phy-ctrl10 1 pad-cal-interval @@ -418,6 +392,7 @@ 0 mc-ck-pd 0 mc-ac-d outbits +[then] phy-ctrl3 h# 2000 phy-res \ Reserved, but Marvell spreadsheet sets it @@ -426,30 +401,30 @@ 0 dq-oen-extend 0 dq-oen-dly 0 rd-ext-dly -4 phy-rfifo-rptr-dly-val \ Tune me !!! -4 dq-ext-dly \ Tune me !!! +3 phy-rfifo-rptr-dly-val \ Tune me !!! +3 dq-ext-dly \ Tune me !!! outbits phy-ctrl7 1 phy-qs-vref-sel -b# 1111 phy-dq-zpdrv -b# 1111 phy-dq-zndrv +b# 0111 phy-dq-zpdrv +b# 0111 phy-dq-zndrv b# 1000 phy-dq-zptrm b# 0100 phy-dq-zntrm -b# 1000 phy-dq-znr -b# 0100 phy-dq-zpr +b# 0111 phy-dq-znr +b# 1001 phy-dq-zpr b# 10 phy-dq-vref-sel 0 phy-dq-zd 1 phy-dq-mode outbits phy-ctrl8 -b# 1111 phy-adcm-zpdrv -b# 1111 phy-adcm-zndrv +b# 0111 phy-adcm-zpdrv +b# 0111 phy-adcm-zndrv b# 0000 phy-adcm-zptrm b# 0000 phy-adcm-zntrm -b# 1000 phy-adcm-znr -b# 0100 phy-adcm-zpr +b# 0111 phy-adcm-znr +b# 1001 phy-adcm-zpr 0 phy-adcm-zd outbits @@ -463,45 +438,63 @@ 0 phy-wc-qs-dly 0 phy-wck-ac-dly 0 phy-wck-ck-dly -b# 1000 phy-ck-znr -b# 0100 phy-ck-zpr +b# 0111 phy-ck-znr +b# 0111 phy-ck-zpr outbits phy-ctrl13 -2 dll-resrt-timer +d# 13 dll-resrt-timer 0 dll-update-stall-mc-dis -d# 16 dll-delay-test -d# 08 dll-phsel -1 dll-auto-manual-up +0 dll-delay-test +d# 04 dll-phsel +0 dll-auto-manual-up 0 dll-auto-update-en 0 dll-test-en 0 dll-bypass-en outbits phy-dll-ctrl1 -d# 16 dll-delay-test -d# 8 dll-phsel +0 dll-delay-test +d# 4 dll-phsel 0 dll-auto-update-en 0 dll-test-en 0 dll-bypass-en outbits phy-dll-ctrl2 -d# 16 dll-delay-test -d# 8 dll-phsel +0 dll-delay-test +d# 4 dll-phsel 0 dll-auto-update-en 0 dll-test-en 0 dll-bypass-en outbits phy-dll-ctrl3 -d# 16 dll-delay-test -d# 8 dll-phsel +0 dll-delay-test +d# 4 dll-phsel 0 dll-auto-update-en 0 dll-test-en 0 dll-bypass-en outbits +\ Assert DLL reset +phy-ctrl14 +0 phy-sync-en +0 dll-update-en +1 phy-dll-rst +0 phy-pll-rst +0 dll-update-en-static +outbits + +\ Release DLL reset and enable update +phy-ctrl14 +0 phy-sync-en +1 dll-update-en +0 phy-dll-rst +0 phy-pll-rst +0 dll-update-en-static +outbits + phy-ctrl-wl-select 0 phy-wl-dqs-recen-dqs 0 phy-wl-cs-sel

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[commit] r2351 - cpu/arm/olpc/1.75
by repository service 14 Jul '11

14 Jul '11

Author: wmb Date: Thu Jul 14 01:12:07 2011 New Revision: 2351 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2351 Log: Fixed a formatting typo. No semantic change. Modified: cpu/arm/olpc/1.75/lcd.fth Modified: cpu/arm/olpc/1.75/lcd.fth ============================================================================== --- cpu/arm/olpc/1.75/lcd.fth Thu Jul 14 01:11:19 2011 (r2350) +++ cpu/arm/olpc/1.75/lcd.fth Thu Jul 14 01:12:07 2011 (r2351) @@ -27,7 +27,7 @@ h# 01330133 h# 13c lcd! \ Panel VSYNC Pulse Pixel Edge Control clkdiv h# 1a8 lcd! \ Clock divider \ h# 08021100 h# 190 lcd! \ DMA CTRL 0 - enable DMA, 24 bpp mode - h# 08001100 h# 190 lcd! \ DMA CTRL 0 - enable DMA, 16 bpp mode + h# 08001100 h# 190 lcd! \ DMA CTRL 0 - enable DMA, 16 bpp mode ; : normal-hsv ( -- )

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[commit] r2350 - cpu/arm/olpc/1.75
by repository service 14 Jul '11

14 Jul '11

Author: wmb Date: Thu Jul 14 01:11:19 2011 New Revision: 2350 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2350 Log: OLPC XO-1.75 - new EC version 4.0.2.00 Modified: cpu/arm/olpc/1.75/ec-version.fth Modified: cpu/arm/olpc/1.75/ec-version.fth ============================================================================== --- cpu/arm/olpc/1.75/ec-version.fth Thu Jul 14 01:08:39 2011 (r2349) +++ cpu/arm/olpc/1.75/ec-version.fth Thu Jul 14 01:11:19 2011 (r2350) @@ -1,5 +1,5 @@ \ The EC microcode -macro: EC_VERSION 4_0_1_03 +macro: EC_VERSION 4_0_2_00 \ Alternate command for getting EC microcode, for testing new versions. \ Temporarily uncomment the line and modify the path as necessary

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[commit] r2349 - cpu/arm/olpc/1.75/build
by repository service 14 Jul '11

14 Jul '11

Author: wmb Date: Thu Jul 14 01:08:39 2011 New Revision: 2349 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2349 Log: svn ignore Modified: cpu/arm/olpc/1.75/build/ (props changed)

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[commit] r2348 - cpu/arm/mmp2
by repository service 14 Jul '11

14 Jul '11

Author: wmb Date: Thu Jul 14 01:07:54 2011 New Revision: 2348 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2348 Log: Checked in some experimental code for testing the speed of MMP2 memory to memory DMA; it serves as an example for how to drive said hardware. Added: cpu/arm/mmp2/mdma.fth Added: cpu/arm/mmp2/mdma.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/mdma.fth Thu Jul 14 01:07:54 2011 (r2348) @@ -0,0 +1,71 @@ +purpose: Test code to determine the speed of MMP2 memory to memory DMA + +\ Copy from cache to cache - 1.3 GB/sec +\ Copy from memory to memory - 323 MB/sec +\ DMA from memory to memory - 425 MB/sec +\ Read from cache (address constant) 4.2 GB/sec +\ Read from memory (advancing address) 390 MB/sec + +h# d42a.0a00 value mdma0-base + +: mdma! ( n offset -- ) mdma0-base + l! ; +: mdma@ ( offset -- n ) mdma0-base + l@ ; + +h# 0010.0000 constant mdma-ram +h# ffc0 constant /mdma-buf +mdma-ram constant mdma-desc0 +h# 10 constant /dma-desc + +\ Descriptor format: +\ Byte count +\ Source +\ Destination +\ link + +: set-descriptor ( next dest source length adr -- ) + >r r@ l! r@ la1+ l! r@ 2 la+ l! r> 3 la+ l! +; + +code cmake-test-ring ( src-adr dst-adr len desc -- ) + \ tos: desc + pop r4,sp \ r4: Total length + pop r2,sp \ r2: dst + pop r1,sp \ r1: src + set r0,#0xffc0 + begin + add r3,tos,#0x10 + stmia tos!,{r0,r1,r2,r3} + inc r1,r0 + inc r2,r0 + decs r4,r0 + 0<= until + \ Go back to last descriptor + dec tos,#0x10 + mov r3,#0 + str r3,[tos,#0x0c] \ Last link is 0 + inc r4,r0 + str r4,[tos] \ Fixup last length + pop tos,sp +c; +0 value dst-adr +0 value src-adr +0 value desc-adr +: make-test-ring ( src-adr dst-adr len -- ) + swap to dst-adr swap to src-adr + mdma-desc0 to desc-adr + 0 ?do + desc-adr /dma-desc + dst-adr i + src-adr i + /mdma-buf desc-adr set-descriptor + desc-adr /dma-desc + to desc-adr + /mdma-buf +loop + + desc-adr /dma-desc - to desc-adr + 0 desc-adr 3 la+ l! \ Put null in last link + + mdma-desc0 h# 30 mdma! \ Link to first descriptor +; +: start-test-ring ( -- ) +\ 8 h# d428.2864 l! \ Enable DMA clock + 1 h# 80 mdma! \ Enable DMA completion interrupts + h# 0000.3d80 h# 40 mdma! \ fetch next, enable, chain, 32 bytes, inc dest, inc src +; +: abort-test-ring ( -- ) h# 10.0000 h# 40 mdma! ;

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[commit] r2347 - cpu/arm/mmp2
by repository service 12 Jul '11

12 Jul '11

Author: wmb Date: Tue Jul 12 11:26:19 2011 New Revision: 2347 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2347 Log: Checked in some demonstration/test code for the Marvel MMP2 internal RTC. Added: cpu/arm/mmp2/rtc.fth Added: cpu/arm/mmp2/rtc.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/rtc.fth Tue Jul 12 11:26:19 2011 (r2347) @@ -0,0 +1,26 @@ +purpose: Driver for MMP2 internal RTC + +\ This code was written as a test/demonstration of using +\ the MMP2 internal RTC to generate alarm interrupts. +\ It is not currently used by anything, and should it +\ ever be needed, it should be put in a device node. + +: int5-mask! ( value -- ) h# d428.216c l! ; +: int5-mask@ ( -- value ) h# d428.216c l@ ; +: int5-status@ ( -- value ) h# d428.2154 l@ ; +: enable-rtc ( -- ) h# 81 h# d401.5000 l! ; +: soc-rtc@ ( offset -- value ) h# d401.0000 + l@ ; +: soc-rtc! ( value offset -- value ) h# d401.0000 + l! ; +: take-alarm ( -- ) + ." Alarm fired" cr + 0 8 soc-rtc! + int5-mask@ 1 or int5-mask! \ Mask alarm +; +: alarm-in-5 ( -- ) + enable-rtc \ Turn on clocks + int5-mask@ 1 invert and int5-mask! \ Unmask alarm + 0 soc-rtc@ d# 5 + 4 soc-rtc! \ Set alarm for 5 seconds from now + 7 8 soc-rtc! \ Ack old interrupts and enable new ones + ['] take-alarm 5 interrupt-handler! + 5 enable-interrupt +;

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[commit] r2346 - cpu/arm/mmp2
by repository service 12 Jul '11

12 Jul '11

Author: wmb Date: Tue Jul 12 11:17:29 2011 New Revision: 2346 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2346 Log: Checked in a file containing complex code for setting up the clocks on an MMP2. Might be useful some day; although much simpler code is currently in use. Added: cpu/arm/mmp2/clocks-complex.fth Added: cpu/arm/mmp2/clocks-complex.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/clocks-complex.fth Tue Jul 12 11:17:29 2011 (r2346) @@ -0,0 +1,308 @@ +purpose: A complex way to do MMP2 clock frequency setting based on Marvell code + +\ Our current chip_id is 00a0.a610 and stepping is 0000.4131 (A1) + +\ vcc pclk pdclk baclk xpclk dclk aclk name +create operating-points +decimal +1230 , 100 , 100 , 100 , 100 , 400 , 100 , \ "Ultra Low MIPS" +1230 , 200 , 200 , 200 , 200 , 400 , 200 , \ "Low MIPS" +1280 , 400 , 200 , 200 , 200 , 400 , 200 , \ "Video M MIPS" +1300 , 800 , 400 , 400 , 400 , 400 , 266 , \ "Video H MIPS" +1350 , 1001 , 500 , 500 , 500 , 400 , 266 , \ "Super H MIPS" +0 , +hex + +0 [if] +1300 , 800 , 400 , 400 , 400 , 400 , 200 , \ "Video H MIPS" - Z0/Z1 settings +1300 , 624 , 312 , 312 , 312 , 312 , 156 , \ "624MHz" - only for Z0 and Z1 steppings + + pj4-cc sp-cc fccr cgr pj4-cc-oct sp-cc-oct + cur 18fd96d9 8fd8241 3077313331 1077301101 + old 78fd8248 8fd8248 7077301110 1077301110 17.077.301.101 + cvr52ADXBCP 52ADXBpP +ok d# 100 find-op new-reg-values .s clear 878b86c3 88b86c3 800000 a000 20742703303 1042703303 +ok d# 200 find-op new-reg-values .s clear 87898241 8898241 800000 a000 20742301101 1042301101 +ok d# 400 find-op new-reg-values .s clear 87898240 8898240 800000 a000 20742301100 1042301100 +ok d# 800 find-op new-reg-values .s clear 87890240 8890240 20800000 8000 20742201100 1042201100 +ok d# 1001 find-op new-reg-values .s clear 87890240 8890240 40800000 c000 20742201100 1042201100 +[then] + +\ IDLE, EXTIDLE, APPS_IDLE, APPS_SLEEP, SYS_SLEEP all have vcc=1280 + +0 value 'op +: pclk ( -- mhz ) 'op 1 na+ @ ; +\ : pdclk ( -- mhz ) 'op 2 na+ @ ; \ This is effectively unused +: baclk ( -- mhz ) 'op 3 na+ @ ; +: xpclk ( -- mhz ) 'op 4 na+ @ ; +: dclk ( -- mhz ) 'op 5 na+ @ ; +: aclk ( -- mhz ) 'op 6 na+ @ ; +: datarate ( -- mhz ) dclk 2* ; + +: ~= ( n1 n2 -- flag ) - -2 2 between ; +: find-op ( mhz -- ) + operating-points begin dup @ while ( mhz adr ) + 2dup na1+ @ ~= if ( mhz adr ) + to 'op drop exit ( -- ) + then ( mhz adr ) + 7 na+ ( mhz adr' ) + repeat ( mhz adr ) + true abort" Can't find operating point" +; + +0 value old-dclk +0 value new-fccr +0 value pll-pj4-frequency +0 value pll-ad-frequency +0 value new-cgr + +: set-field ( val bits bit# -- val' ) lshift or ; +: >bit ( bit# -- ) 1 swap lshift ; +: set-bit ( val bit# -- val' ) >bit or ; + +create frequencies d# 400 , d# 800 , 0 , d# 26 , +: fccr>frequency ( source-id -- mhz ) frequencies swap na+ @ ; +: 'pll2-frequency ( -- adr ) frequencies 2 na+ ; + +create cgr-masks d# 13 >bit , d# 15 >bit , d# 14 >bit , 0 , +: fccr>cgr-mask ( source-id -- mhz ) cgr-masks swap na+ @ ; + +: frequency>fccr ( mhz -- fccr-bits ) + dup d# 26 = if drop 3 exit then \ Special case for VCXO frequency + d# 800 over mod 3 < if ( mhz ) \ Close to a divisor of 800 ? + d# 400 <= if 0 else 1 then ( fccr-bits ) + else ( mhz ) + 'pll2-frequency @ if ( mhz ) + drop ( ) + else ( mhz ) + 'pll2-frequency ! ( ) + then ( ) + 2 ( fccr-bits ) + then ( fccr-bits ) +; + +: mhz>source-frequency ( mhz fccr-bit# -- source-frequency ) + >r frequency>fccr ( fccr-bits r: fccr-bit# ) + dup r> lshift new-fccr or to new-fccr ( fccr-bits ) + dup fccr>cgr-mask new-cgr or to new-cgr ( fccr-bits ) + fccr>frequency ( source-frequency ) +; +: choose-pclk-source ( -- ) + pclk d# 29 mhz>source-frequency to pll-pj4-frequency ( ) +\ clip-pj4-clocks +; + +: choose-dclk-source ( -- ) + datarate d# 23 mhz>source-frequency to pll-ad-frequency ( ) +\ clip-ad-clocks +; + +\ The clock sources have been selected, so pll-pj4-frequency and pll-ad-frequency are valid +\ Calculate the various divisors and insert them into the appropriate fields for the +\ two clock control registers. +: compute-new-cc-regs ( -- pj4-cc sp-cc ) + 0 ( cc-reg ) + pclk if pll-pj4-frequency pclk / 1- 0 set-field then ( cc-reg' ) + xpclk if pll-pj4-frequency xpclk / 1- 9 set-field then ( cc-reg' ) + pll-pj4-frequency baclk / 1- baclk if 6 else 3 then set-field ( cc-reg' ) \ Either BA_CLK (6) or CS_CLK (3) + + datarate if pll-ad-frequency datarate / 1- d# 12 set-field then ( cc-reg' ) + aclk if pll-ad-frequency aclk / 1- d# 15 set-field then ( cc-reg' ) + +\ The lines following this block force both async bits to be set, so this conditional setting is irrelevant +\ pdclk datarate <> if d# 19 set-bit then \ Async2 if pdclock2 != DDRClk +\ baclk aclk <> if d# 23 set-bit then \ Async5 if baclk2 != aclk + + d# 19 set-bit ( cc-reg' ) \ PMUA_CC_MOH_ASYNC2 + d# 23 set-bit ( cc-reg' ) \ PMUA_CC_MOH_ASYNC5 + + \ Write a subset of the fields to the SP's clock control register before finishing the value for the PJ4's CC reg + dup d# 27 >bit or swap ( sp-cc-reg pj4-cc-reg ) \ PMUA_CC_SEA_SEA_ALLOW_SPD_CHG bit + others in PMUA_CC_SP + + pclk 0<> baclk 0<> or ( pdclk 0<> or ) xpclk 0<> or if d# 24 set-bit then ( cc-reg' ) \ PMUA_CC_MOH_MOH_FREQ_CHG_REQ + datarate if d# 25 set-bit then ( sp-cc-reg pj4-cc-reg' ) \ PMUA_CC_MOH_DDR_FREQ_CHG_REQ + aclk if d# 26 set-bit then ( sp-cc-reg pj4-cc-reg' ) \ PMUA_CC_MOH_BUS_FREQ_CHG_REQ +[ifdef] notdef + dup h# 0700.0000 and if d# 27 set-bit then ( sp-cc-reg pj4-cc-reg' ) +[then] + d# 31 set-bit ( sp-cc-reg pj4-cc-reg' ) \ PMUA_CC_MOH_MOH_RD_ST_CLEAR + swap ( pj4-cc-reg sp-cc-reg ) +; + +\ Assumes that 'op already points to an operating point table +: new-reg-values ( -- pj4-cc sp-cc fccr cgr ) + 0 to new-fccr 0 to new-cgr 'pll2-frequency off + choose-pclk-source + choose-dclk-source + +\ I think this write is deferred until the DDR clock setting step +\ writel(fccr, info->pmum_base + FCCR_OFF); + + compute-new-cc-regs ( pj4-cc sp-cc ) + new-fccr new-cgr ( pj4-cc sp-cc fccr cgr ) +; + +\ Beginning of section that accesses the hardware + +: +pmua ( -- adr ) h# d428.2800 + ; +: +pmum ( -- adr ) h# d405.0000 + ; + +: pmum-pll2cr ( -- adr ) h# 34 +pmum ; +: pmum-pll2-ctrl1 ( -- adr ) h# 414 +pmum ; +: get-pll2-frequency ( -- mhz ) + pmum-pll2cr l@ ( regval ) \ PMUM_PLL2CR + dup d# 19 5 bits ( regval refdiv ) + swap d# 10 9 bits ( refdiv fbdiv ) + 2+ d# 26 * ( refdiv numerator ) + swap 2+ / ( mhz ) +; +: reg-set ( mask -- ) >r r@ l@ or r> l! ; +: reg-clr ( mask -- ) >r r@ l@ swap invert and r> l! ; + +4 constant refdiv \ 4 is the only reference divisor value that is mentioned in the documentation + +: setup-pll2 ( freq -- ) + refdiv 2+ * d# 26 rounded-/ ( fbdiv ) + 1 d# 29 lshift pmum-pll2-ctrl1 reg-clr ( fbdiv ) \ make sure pll2 is in reset + + + pmum-pll2cr l@ ( fbdiv val ) + h# 100 invert and ( fbdiv val' ) \ PMUM_PLL2CR_PLL2_SW_EN off + dup pmum-pll2cr l! ( fbdiv val ) + + h# 0007.fc00 invert and refdiv d# 19 lshift or ( fbdiv val' ) + h# 00f8.0000 invert and swap d# 10 lshift or ( val' ) + + h# 200 or ( val' ) \ PMUM_PLL2CR_CTRL + dup pmum-pll2cr l! ( val ) + + h# 100 or ( val ) + pmum-pll2cr l! ( ) \ PMUM_PLL2CR_PLL2_SW_EN on + + 1 d# 29 lshift pmum-pll2-ctrl1 reg-set ( ) \ pll2 out of reset + + d# 20 ms \ C code uses 2M spins +; + +: ?change-pll2-frequency ( -- ) + 'pll2-frequency @ ?dup if ( mhz ) + dup get-pll2-frequency <> if ( mhz ) + setup-pll2 ( ) + else ( mhz ) + drop ( ) + then ( ) + then ( ) +; + +[ifdef] later +: set-sram-table ( table-adr table# -- ) + 4 lshift h# 8000.0000 or ( table-adr common-bits ) + #sram-table 0 do ( table-adr common-bits ) + over i 8 * + ( table-adr common-bits table-entry-adr ) + dup l@ h# c20 dmcu! ( table-adr common-bits table-entry-adr ) + la1+ l@ h# c30 dmcu! ( table-adr common-bits ) + over i or h# c00 dmcu! ( common-bits table-adr ) + loop ( table-adr common-bits ) + 2drop ( ) +; +: x-do-fcs ( cc-reg fccr dclk -- ) + dup old-dclk = if ( cc-reg fccr dclk ) + \ There is no need to do DDR recal if dclk is unchanged + drop ( cc-reg fccr ) + 0 ( cc-reg fccr pmua_mc_par_ctrl-val ) + else ( cc-reg fccr dclk ) + dup to old-dclk ( cc-reg fccr dclk ) + choose-ddr-table 0 set-sram-table ( cc-reg fccr ) + 4 ( cc-reg fccr pmua_mc_par_ctrl-val ) + then to pmua_mc_par_ctrl-val ( cc-reg fccr ) + + +\ STUFF +; +[then] +: do-fcs ( cc-reg fccr dclk -- ) + drop ." FCCR " .x ." CCR " .x cr +; + +: current-dclk ( -- mhz ) + 8 +pmum l@ d# 23 rshift 7 and fccr>frequency ( source-mhz ) + 4 +pmua l@ d# 12 rshift 7 and 1+ / +; + +: PMUcore2_hw_fc_seq ( -- ) + current-dclk to old-dclk +\ get-pll2-frequency to old-pll2-frequency +\ pll2-old-frequency pclk min to new-pll2-frequency + + d# 31 >bit 4 +pmua reg-clr \ PMUA_CC_MOH_MOH_RD_ST_CLEAR - clears PJ_RD_STATUS to allow frequency changing + + d# 21 >bit h# 88 +pmua reg-set \ Omit this on Z stepping - this is an undocumented bit in an undocumented debug register + + 1 >bit h# 98 +pmua reg-set \ PMUA_MOH_IMR_MOH_FC_INTR_MASK bit in PMUA_PJ_IMR register + + begin + 4 +pmua l@ d# 24 >bit and \ PMUA_DM_CC_MOH_SEA_RD_STATUS bit in DM_CC_MOH register + 0= until + + new-reg-values ( pj4-cc sp-cc fccr cgr ) + + ?change-pll2-frequency ( pj4-cc sp-cc fccr cgr ) + + h# 1024 +pmum l! ( pj4-cc sp-cc fccr ) + swap 0 +pmua l! ( pj4-cc-reg fccr ) + dclk do-fcs ( ) + +[ifdef] notdef + 2 >bit h# b4 +pmua reg-clr \ MC_FC_SLP_EN bit in PMUA_MC_SLP_REQ_PJ register +[then] + + d# 31 >bit 4 +pmua reg-clr \ PMUA_CC_MOH_MOH_RD_ST_CLEAR (the documentation is unclear - is this bit write 1 to clr?) +; + +0 [if] +0 value new-pll2-frequency +0 value old-pll2-frequency +: clip-pj4-clocks ( -- ) + pll-pj4-frequency pclk min to pclk ( ) +\ pll-pj4-frequency pdclk min to pdclk ( ) + pll-pj4-frequency baclk min to baclk ( ) + pll-pj4-frequency xpclk min to xpclk ( ) +; +: clip-ad-clocks ( -- ) + pll-ad-frequency aclk min to aclk ( ) + pll-ad-frequency datarate min to datarate ( ) +; + +: old-choose-pclk-source ( -- ) + pclk case + d# 100 of d# 400 d# 13 >bit 0 endof + d# 200 of d# 400 d# 13 >bit 0 endof + d# 400 of d# 400 d# 13 >bit 0 endof + d# 800 of d# 800 d# 15 >bit 1 endof + ( default ) + old-pll2-frequency new-pll2-frequency <> if + new-pll2-frequency setup-pll2 + then + >r new-pll2-frequency d# 14 >bit 2 r> + endcase ( pll-pj4-frequency acgr-bits fccr-bits ) + + d# 29 lshift to new-fccr ( pll-pj4-frequency acgr-bits ) + new-cgr or to new-cgr ( pll-pj4-frequency ) + to pll-pj4-frequency ( ) +\ clip-pj4-clocks +; +: old-choose-dclk-source ( -- ) + datarate case + d# 100 of d# 400 d# 13 >bit 0 endof + d# 200 of d# 400 d# 13 >bit 0 endof + d# 400 of d# 400 d# 13 >bit 0 endof + d# 800 of d# 800 d# 15 >bit 1 endof + ( default ) >r pll-pj4-frequency d# 14 >bit 2 r> + endcase ( pll-ad-frequency acgr-bits fccr-bits ) + + new-fccr over d# 23 set-field to new-fccr ( pll-ad-frequency acgr-bits ) + new-cgr or to new-cgr ( pll-ad-frequency ) + to pll-ad-frequency ( ) +\ clip-ad-clocks +; +[then]

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[commit] r2345 - forth/lib
by repository service 12 Jul '11

12 Jul '11

Author: wmb Date: Tue Jul 12 11:15:11 2011 New Revision: 2345 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2345 Log: Added a couple of tools to forth/lib for handling WinCE binaries. Not used by any standard builds. Added: forth/lib/dumpcebin.fth forth/lib/makecebin.fth Added: forth/lib/dumpcebin.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ forth/lib/dumpcebin.fth Tue Jul 12 11:15:11 2011 (r2345) @@ -0,0 +1,41 @@ +purpose: Show the sections of a WinCE .bin file + +h# 60 constant /buf +/buf buffer: secbuf +: +buf ( offset -- adr ) secbuf + ; +: sec@ ( offset -- l ) +buf l@ ; + +0 value section-len +: .section ( offset -- offset' ) + ." File offset: " dup 8 u.r + dup ifd @ fseek ( offset ) + secbuf d# 12 ifd @ fgets d# 12 <> abort" read failure" + 0 sec@ 0= if + ." Final record: " 4 sec@ 8 u.r ." " 8 sec@ 8 u.r cr + exit + then + + ." Start " 0 sec@ 8 u.r ." Length " 4 sec@ 8 u.r ." Sum " 8 sec@ 8 u.r cr + 4 sec@ to section-len + secbuf h# 60 section-len min ifd @ fgets drop + secbuf h# 60 section-len min ldump cr ( offset ) + d# 12 + section-len + +; + +: (dump-bin) ( filename$ -- ) + hex + $read-open + secbuf h# f ifd @ fgets h# f <> abort" Signature read failure" + secbuf " B000FF"n" comp abort" Bad signature" + + ." Load start " 7 sec@ 8 u.r ." Total length " h# b sec@ 8 u.r cr cr + + h# f begin ifd @ ftell ifd @ fsize < while ( offset ) + .section ( offset' ) + repeat ( offset ) + drop ( ) + ifd @ fclose +; +: dump-bin ( "filename" -- ) + safe-parse-word (dump-bin) +; Added: forth/lib/makecebin.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ forth/lib/makecebin.fth Tue Jul 12 11:15:11 2011 (r2345) @@ -0,0 +1,39 @@ +purpose: Wrap an OFW image in a WinCE ".bin" file format + +h# 100000 constant ofw-load-address +h# 100000 constant ofw-entry-address + +: put-long ( l -- ) + lbsplit swap 2swap swap ( hi hmid lmid lo ) + 4 0 do ofd @ fputc loop +; + +: make-bin-file ( "in-filename" "out-filename" -- ) + reading writing + + " B000FF"n" ofd @ fputs \ Signature + ofw-load-address put-long \ Lowest load address + ifd @ fsize put-long \ Total size + + ofw-load-address put-long \ Section load address - offset h# 0f + ifd @ fsize put-long \ Total size offset h# 13 + 0 put-long \ Checksum, will be patched later - offset h# 17 + + 0 ( sum ) + begin ( sum ) + ifd @ fgetc ( sum char ) + dup -1 <> ( sum char more? ) + while ( sum char ) + dup ofd @ fputc ( sum char ) + + ( sum' ) + repeat ( sum ) + + \ Final record with entry address + 0 put-long ( ) + ofw-entry-address put-long ( ) + 0 put-long ( ) + + h# 17 ofd @ fseek ( sum ) + put-long ( ) + ofd @ fclose ( ) +;

1 0

[commit] r2344 - clients/emacs/arm
by repository service 12 Jul '11

12 Jul '11

Author: wmb Date: Tue Jul 12 11:09:52 2011 New Revision: 2344 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2344 Log: svn ignore Modified: clients/emacs/arm/ (props changed) clients/emacs/arm/Makefile Modified: clients/emacs/arm/Makefile ============================================================================== --- clients/emacs/arm/Makefile Tue Jul 12 11:05:21 2011 (r2343) +++ clients/emacs/arm/Makefile Tue Jul 12 11:09:52 2011 (r2344) @@ -33,6 +33,7 @@ emacs: emacs.elf @$(STRIP) $< -o $@ + @rm emacs.elf emacs.elf: $(LIBDIR)/start.o $(OFILES) $(LIBS) Makefile emacs.lds $(LD) $(LFLAGS) -o $@ $(LIBDIR)/start.o $(OFILES) $(LIBS) -L$(GLIBDIR) -lgcc

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