openfirmware January 2015

openfirmware@openfirmware.info

4 participants
17 discussions

[commit] r3758 - dev/olpc/dcon
by repository service 06 Jan '15

06 Jan '15

Author: quozl Date: Tue Jan 6 04:55:38 2015 New Revision: 3758 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3758 Log: OLPC XO-4 - dcon-setup, lower drive strength for DETTL clock and data signals. #12852. Modified: dev/olpc/dcon/mmp2dcon.fth Modified: dev/olpc/dcon/mmp2dcon.fth ============================================================================== --- dev/olpc/dcon/mmp2dcon.fth Mon Jan 5 09:37:03 2015 (r3757) +++ dev/olpc/dcon/mmp2dcon.fth Tue Jan 6 04:55:38 2015 (r3758) @@ -237,6 +237,9 @@ h# 0101 h# 41 dcon! h# 0101 h# 42 dcon! +[ifdef] mmp3 + h# 1830 h# 4c dcon! \ low drive strength for DETTL clock and data +[then] h# 12 mode! scanint-set false

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On Raspberry Pi
by Mark Morgan Lloyd 05 Jan '15

05 Jan '15

Is it possible to put OpenFirmware on an SD card and use it to boot off e.g. a USB-attached mass storage device or using TFTP over a LAN? -- Mark Morgan Lloyd markMLl .AT. telemetry.co .DOT. uk [Opinions above are the author's, not those of his employers or colleagues]

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[commit] r3757 - cpu/arm/mmp3
by repository service 05 Jan '15

05 Jan '15

Author: quozl Date: Mon Jan 5 09:37:03 2015 New Revision: 3757 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3757 Log: OLPC XO-4 - trim enable-smp based on kernel patch f37e149 on arm-3.5-volansys branch by Darshan Prajapati; remove early initialisation instructions from spin, remove storage LED GPIO set, and don't enable all peripheral clocks. Modified: cpu/arm/mmp3/dramrecal.fth Modified: cpu/arm/mmp3/dramrecal.fth ============================================================================== --- cpu/arm/mmp3/dramrecal.fth Sun Jan 4 23:12:10 2015 (r3756) +++ cpu/arm/mmp3/dramrecal.fth Mon Jan 5 09:37:03 2015 (r3757) @@ -288,30 +288,6 @@ \ a reset handler for second core code spin - mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0xd3 - msr cpsr,r0 - - mov r0, #0 \ set up for MCR - mcr p15, 0, r0, cr8, cr7, 0 \ invalidate TLBs - mcr p15, 0, r0, cr7, cr5, 0 \ invalidate icache - mcr p15, 0, r0, cr7, cr5, 6 \ invalidate BP array - mcr p15, 0, r0, cr7, cr10, 4 \ DSB - mcr p15, 0, r0, cr7, cr5, 4 \ ISB - - mrc p15, 0, r0, cr1, cr0, 0 - bic r0, r0, #0x00002000 \ clear bits 13 (--V-) - bic r0, r0, #0x00000007 \ clear bits 2:0 (-CAM) - orr r0, r0, #0x00000002 \ set bit 1 (--A-) Align - orr r0, r0, #0x00000800 \ set bit 11 (Z---) BTB - bic r0, r0, #0x00001000 \ set bit 12 (I) I-cache - mcr p15, 0, r0, cr1, cr0, 0 - - set r1,#0xd4019018 \ physical address of gpio set register - mov r0,#0x400 \ mask for port bit, storage led - str r0,[r1] - set r1,#0xd4282c24 \ address of __sw_branch register mov r0,#0x0 str r0,[r1] \ clear register @@ -334,11 +310,6 @@ h# e000.0000 h# 94 ciu! \ set periphbase_addr h# ffff.e001 h# 9c ciu! \ set periphbase_size, set periphbase_enable - \ enable all clocks - h# ffff.ffff h# 1024 mpmu! \ MPMU_CGR_PJ - h# 3.ffff h# dc pmua! \ PMUA_GLB_CLK_CTRL - - h# 2000.0000 h# 200 pmua! \ PMUA_PJ_IDLE_CFG2, stay powered on WFI 0 h# d428.2c24 l! \ clear __sw_branch register h# 0200.0000 cc2-clr d# 1 ms h# 0200.0000 cc2-set \ reset mpcore2 ;

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[commit] r3756 - cpu/arm/olpc/4.0
by repository service 04 Jan '15

04 Jan '15

Author: quozl Date: Sun Jan 4 23:12:10 2015 New Revision: 3756 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3756 Log: Q7C01 Modified: cpu/arm/olpc/4.0/fw-version.fth Modified: cpu/arm/olpc/4.0/fw-version.fth ============================================================================== --- cpu/arm/olpc/4.0/fw-version.fth Sun Jan 4 23:11:43 2015 (r3755) +++ cpu/arm/olpc/4.0/fw-version.fth Sun Jan 4 23:12:10 2015 (r3756) @@ -1,7 +1,7 @@ \ The overall firmware revision macro: FW_PREFIX Q7 macro: FW_MAJOR C -macro: FW_MINOR 00 +macro: FW_MINOR 01 \ Create a 2-character build/fw-suffix file to personalize your test builds " fw-suffix" $file-exists? [if]

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[commit] r3755 - in cpu: arm/mmp3 x86/pc/olpc/sstools
by repository service 04 Jan '15

04 Jan '15

Author: quozl Date: Sun Jan 4 23:11:43 2015 New Revision: 3755 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3755 Log: OLPC XO-4 - source formatting, fix use of irqdef undone in r3753 (change was made in irqdef later) Modified: cpu/arm/mmp3/gic.fth cpu/x86/pc/olpc/sstools/xpm.fth Modified: cpu/arm/mmp3/gic.fth ============================================================================== --- cpu/arm/mmp3/gic.fth Fri Jan 2 01:55:02 2015 (r3754) +++ cpu/arm/mmp3/gic.fth Sun Jan 4 23:11:43 2015 (r3755) @@ -15,16 +15,17 @@ : make-gmux-node ( statreg maskreg irq# #irqs ) new-device - " interrupt-controller" name ( maskreg statreg irq# #irqs ) - " mrvl,intc-nr-irqs" integer-property ( maskreg statreg irq# ) + " interrupt-controller" name ( maskreg statreg irq# #irqs ) + " mrvl,intc-nr-irqs" integer-property ( maskreg statreg irq# ) 0 encode-int rot encode-int encode+ 1 encode-int encode+ - " interrupts" property ( maskreg statreg ) + " interrupts" property ( maskreg statreg ) >r 4 encode-reg r> 4 encode-reg encode+ " reg" property ( ) " mrvl,mmp3-mux-intc" +compatible 0 0 " interrupt-controller" property 1 " #interrupt-cells" integer-property - " mux status" encode-string " mux mask" encode-string encode+ " reg-names" property + " mux status" encode-string + " mux mask" encode-string encode+ " reg-names" property finish-device ; @@ -67,77 +68,77 @@ " interrupts" property ; -\ modify all irqs to use 3 cells instead of 1 -dev /timer d irqdef dend -\ dev /wakeup-rtc 1 0 irqdef2 dend -\ dev /thermal b irqdef dend -\ dev /audio 2 irqdef dend -dev /sspa 3 irqdef dend -\ dev /adma@c0ffd800 12 13 irqdef2 dend -\ dev /adma@c0ffd900 14 15 irqdef2 dend -\ dev /camera 1 irqdef dend -dev /ap-sp 28 irqdef dend -dev /usb 2c irqdef dend -dev /ec-spi - 0 encode-int - h# 14 encode-int encode+ - h# 4 encode-int encode+ - " interrupts" property -dend -\ dev /sd/sdhci@d4217000 0 irqdef dend -dev /sd/sdhci@d4280000 27 irqdef dend -dev /sd/sdhci@d4281000 35 irqdef dend -dev /sd/sdhci@d4280800 - 0 encode-int - h# 34 encode-int encode+ - h# 4 encode-int encode+ - " interrupts" property -dend -\ dev /gpu 0 2 irqdef2 dend -dev /display 29 irqdef dend -dev /vmeta 1a irqdef dend -dev /flash 0 irqdef dend -dev /uart@d4016000 2e irqdef dend -dev /uart@d4030000 1b irqdef dend -dev /uart@d4017000 1c irqdef dend -dev /uart@d4018000 18 irqdef dend -dev /i2c@d4034000 4 irqdef dend -dev /i2c@d4033000 2 irqdef dend -dev /i2c@d4031000 0 irqdef dend -dev /i2c@d4011000 7 irqdef dend -dev /dma 30 irqdef dend -dev /gpio 31 irqdef dend +\ modify irqs to use 3 cells instead of 1 +dev /timer h# 0d irqdef dend +\ dev /wakeup-rtc h# 01 h# 00 irqdef2 dend +\ dev /thermal h# 0b irqdef dend +\ dev /audio h# 02 irqdef dend +dev /sspa h# 03 irqdef dend +\ dev /adma@c0ffd800 h# 12 h# 13 irqdef2 dend +\ dev /adma@c0ffd900 h# 14 h# 15 irqdef2 dend +\ dev /camera h# 01 irqdef dend +dev /ap-sp h# 28 irqdef dend +dev /usb h# 2c irqdef dend +dev /ec-spi h# 14 irqdef dend +\ dev /sd/sdhci@d4217000 h# 00 irqdef dend +dev /sd/sdhci@d4280000 h# 27 irqdef dend +dev /sd/sdhci@d4281000 h# 35 irqdef dend +dev /sd/sdhci@d4280800 h# 34 irqdef dend +\ dev /gpu h# 00 h# 02 irqdef2 dend +dev /display h# 29 irqdef dend +dev /vmeta h# 1a irqdef dend +dev /flash h# 00 irqdef dend +dev /uart@d4016000 h# 2e irqdef dend +dev /uart@d4030000 h# 1b irqdef dend +dev /uart@d4017000 h# 1c irqdef dend +dev /uart@d4018000 h# 18 irqdef dend +dev /i2c@d4034000 h# 04 irqdef dend +dev /i2c@d4033000 h# 02 irqdef dend +dev /i2c@d4031000 h# 00 irqdef dend +dev /i2c@d4011000 h# 07 irqdef dend +dev /dma h# 30 irqdef dend +dev /gpio h# 31 irqdef dend \ modify all mux irq users to not point to ICU node dev /sd/sdhci@d4217000 - " /interrupt-controller@e0001000/interrupt-controller@184" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@184" encode-phandle + " interrupt-parent" property dend dev /camera@d420a000 - " /interrupt-controller@e0001000/interrupt-controller@1cc" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@1cc" encode-phandle + " interrupt-parent" property dend dev /adma@c0ffd800 - " /interrupt-controller@e0001000/interrupt-controller@128" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@128" encode-phandle + " interrupt-parent" property dend dev /adma@c0ffd900 - " /interrupt-controller@e0001000/interrupt-controller@128" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@128" encode-phandle + " interrupt-parent" property dend dev /thermal - " /interrupt-controller@e0001000/interrupt-controller@188" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@188" encode-phandle + " interrupt-parent" property dend dev /wakeup-rtc - " /interrupt-controller@e0001000/interrupt-controller@154" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@154" encode-phandle + " interrupt-parent" property dend dev /gpu - " /interrupt-controller@e0001000/interrupt-controller@1c0" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@1c0" encode-phandle + " interrupt-parent" property dend dev /i2c@d4034000 - " /interrupt-controller@e0001000/interrupt-controller@158" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@158" encode-phandle + " interrupt-parent" property dend dev /i2c@d4033000 - " /interrupt-controller@e0001000/interrupt-controller@158" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@158" encode-phandle + " interrupt-parent" property dend dev /i2c@d4031000 - " /interrupt-controller@e0001000/interrupt-controller@158" encode-phandle " interrupt-parent" property + " /interrupt-controller@e0001000/interrupt-controller@158" encode-phandle + " interrupt-parent" property dend : mmp3-gic ." mmp3-gic" cr ; \ 92ms Modified: cpu/x86/pc/olpc/sstools/xpm.fth ============================================================================== --- cpu/x86/pc/olpc/sstools/xpm.fth Fri Jan 2 01:55:02 2015 (r3754) +++ cpu/x86/pc/olpc/sstools/xpm.fth Sun Jan 4 23:11:43 2015 (r3755) @@ -10,7 +10,7 @@ \ list of unique colours in frame buffer 0 value ct \ address of table d# 62 value /ct \ entries in table (and alphabet utilisation, @-~) - \ d# 62 is insufficient for menu + \ d# 62 is insufficient for menu h# 0 value nct \ next entry to use in table \ borrowed from screen-ih

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[commit] r3754 - cpu/arm/mmp3
by repository service 02 Jan '15

02 Jan '15

Author: quozl Date: Fri Jan 2 01:55:02 2015 New Revision: 3754 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3754 Log: OLPC XO-4 - enable-smp, review comments, remove unnecessary changes Modified: cpu/arm/mmp3/dramrecal.fth Modified: cpu/arm/mmp3/dramrecal.fth ============================================================================== --- cpu/arm/mmp3/dramrecal.fth Fri Jan 2 00:34:16 2015 (r3753) +++ cpu/arm/mmp3/dramrecal.fth Fri Jan 2 01:55:02 2015 (r3754) @@ -329,14 +329,12 @@ : enable-smp ( -- ) ['] spin >physical 0 hw-install-handler 0 d# 4096 sync-cache - h# 8 cc3-set \ moltres timerclk domain software reset, release - - \ moltres peripheral space configuration register + \ enable mapping of PMR peripherals, so that PGU and GIC can be used, + \ using the moltres peripheral space configuration register h# e000.0000 h# 94 ciu! \ set periphbase_addr h# ffff.e001 h# 9c ciu! \ set periphbase_size, set periphbase_enable \ enable all clocks - h# ffff.ffff h# 0024 mpmu! \ MPMU_CGR_SP h# ffff.ffff h# 1024 mpmu! \ MPMU_CGR_PJ h# 3.ffff h# dc pmua! \ PMUA_GLB_CLK_CTRL

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[commit] r3753 - cpu/arm/mmp3
by repository service 02 Jan '15

02 Jan '15

Author: quozl Date: Fri Jan 2 00:34:16 2015 New Revision: 3753 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3753 Log: OLPC XO-4 - mmp3-gic, switch to using level triggered interrupts, for compatibility with prior use of ICU Modified: cpu/arm/mmp3/gic.fth Modified: cpu/arm/mmp3/gic.fth ============================================================================== --- cpu/arm/mmp3/gic.fth Tue Dec 30 01:53:50 2014 (r3752) +++ cpu/arm/mmp3/gic.fth Fri Jan 2 00:34:16 2015 (r3753) @@ -52,7 +52,7 @@ : irqdef ( irq# -- ) 0 encode-int rot encode-int encode+ - 1 encode-int encode+ + 4 encode-int encode+ " interrupts" property ; @@ -78,11 +78,21 @@ \ dev /camera 1 irqdef dend dev /ap-sp 28 irqdef dend dev /usb 2c irqdef dend -dev /ec-spi 14 irqdef dend +dev /ec-spi + 0 encode-int + h# 14 encode-int encode+ + h# 4 encode-int encode+ + " interrupts" property +dend \ dev /sd/sdhci@d4217000 0 irqdef dend dev /sd/sdhci@d4280000 27 irqdef dend dev /sd/sdhci@d4281000 35 irqdef dend -dev /sd/sdhci@d4280800 34 irqdef dend +dev /sd/sdhci@d4280800 + 0 encode-int + h# 34 encode-int encode+ + h# 4 encode-int encode+ + " interrupts" property +dend \ dev /gpu 0 2 irqdef2 dend dev /display 29 irqdef dend dev /vmeta 1a irqdef dend

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openfirmware January 2015