openfirmware May 2011

openfirmware@openfirmware.info

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[commit] r2202 - cpu/x86/pc/olpc/via
by repository service 19 May '11

19 May '11

Author: wmb Date: Thu May 19 08:11:17 2011 New Revision: 2202 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2202 Log: OLPC XO-1.5 - Altered DSDT to declare only C2, omitting C3 and C4 power states, only for new Rev L and later boards, which fail when coming out of C3 or C4. Added: cpu/x86/pc/olpc/via/dsdt-c2only.dsl Modified: cpu/x86/pc/olpc/via/acpi.fth cpu/x86/pc/olpc/via/dsdt.bth cpu/x86/pc/olpc/via/fw-version.fth cpu/x86/pc/olpc/via/olpc.bth Modified: cpu/x86/pc/olpc/via/acpi.fth ============================================================================== --- cpu/x86/pc/olpc/via/acpi.fth Wed May 18 05:37:42 2011 (r2201) +++ cpu/x86/pc/olpc/via/acpi.fth Thu May 19 08:11:17 2011 (r2202) @@ -285,7 +285,8 @@ \ Copy in the DSDT \ I suppose we could point to it in FLASH - if so don't compress it, \ and fixup the address in the fadt and rechecksum the fadt - " dsdt" find-drop-in 0= abort" No DSDT " ( adr len ) + board-revision h# d78 >= if " dsdt-c2only" else " dsdt" then + find-drop-in 0= abort" No DSDT " ( adr len ) 2dup dsdt-adr swap move free-mem do-acpi-wake wake-adr /do-acpi-wake move Added: cpu/x86/pc/olpc/via/dsdt-c2only.dsl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/x86/pc/olpc/via/dsdt-c2only.dsl Thu May 19 08:11:17 2011 (r2202) @@ -0,0 +1,2597 @@ +// LICENSE_BEGIN +// Copyright (c) 2009 One Laptop per Child, Association, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be +// included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// +// LICENSE_END + +DefinitionBlock ("dsdt-c2only.aml", // AML file name + "DSDT", // Table signature, DSDT + 0x01, // Compliance Revision + "OLPC", // OEM ID + "XO-1.5 ", // Table ID + 0x00000001) // OEM Revision +{ + +// This entity must be present very near the beginning of the DSDT +// so Windows OEM Activation will work. The OEMBIOS.INI file that +// was supplied to Microsoft stipulates that the sequence "OLPC XO" +// will appear within 60 bytes of the address 0xfc000, which is the +// DSDT start address. +Name (VERS, Package (0x02) { + "QUANTACOMPUTER XO-1.5", + "$Id$" +}) + +// OperationRegion (SMIR, SystemIO, 0x042f, 0x01) +// Field (SMIR, ByteAcc, NoLock, Preserve) +// { +// SMIE, 8 +// } +// Method (FRTH, 1, NotSerialized) +// { +// Store(Arg0, SMIE) +// // Type "resume" at the OK prompt to return +// } + +OperationRegion (UART, SystemIO, 0x03f8, 0x08) + +// set to 1 to enable debug output +Name (UDBG, 0) + +Field (UART, ByteAcc, NoLock, Preserve) +{ + UDAT, 8, + UAR1, 8, + UAR2, 8, + UAR3, 8, + UAR4, 8, + USTA, 8, + UAR5, 8 +} + +Method (UPUT, 1, NotSerialized) +{ + If (UDBG) { + While( LEqual (And (USTA, 0x20), Zero) ) { + Stall (99) + } + Store (Arg0, UDAT) + } +} + +Method (UDOT, 1, NotSerialized) +{ + If (UDBG) { + And (ShiftRight (Arg0, 4), 0xF, Local0) + If (LLess (Local0, 10)) { + Add (Local0, 0x30, Local0) // '0' + } Else { + Add (Local0, 0x57, Local0) // 'a' - 10 + } + UPUT (Local0) + + And (Arg0, 0xF, Local0) + If (LLess (Local0, 10)) { + Add (Local0, 0x30, Local0) // '0' + } Else { + Add (Local0, 0x57, Local0) // 'a' - 10 + } + UPUT (Local0) + + UPUT (0x20) + } +} + +OperationRegion(CMS1, SystemIO, 0x74, 0x2) +Field(CMS1, ByteAcc, NoLock, Preserve) { + CMSI, 8, + CMSD, 8 +} + +Method (CMSW, 2) +{ + Store (Arg0, CMSI) + Store (Arg1, CMSD) +} + +// Processor Objects +Scope(\_PR) +{ + Processor(\_PR.CPU0,0x00,0x00000410,0x06) + { + Name(_CST, Package() + { + 1, + Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x414)}, 2, 2, 750}, + }) + } +} + +// System Sleep States +Name(\_S0,Package(){0,0,0,0}) +// Name(\_S1,Package(){4,4,4,4}) // Entering S1 sometimes prevents entry to S3 in Windows +Name(\_S3,Package(){1,1,1,1}) +Name(\_S4,Package(){2,2,2,2}) +Name(\_S5,Package(){2,2,2,2}) + +OperationRegion(\DEBG, SystemIO, 0x80, 0x1) +Field(\DEBG, ByteAcc, NoLock, Preserve) { + DBG1, 8, +} + +// PMIO_RX04 +OperationRegion(\SCIE, SystemIO, 0x0404, 0x2) // Genernal Purpose SCI Enable +Field(\SCIE, ByteAcc, NoLock, Preserve) { + SCIZ, 1, // SCI / SMI enable +} + +OperationRegion(\GPST, SystemIO, 0x0420, 0x2) +Field(\GPST, ByteAcc, NoLock, Preserve) { + GS00,1, // GPI0 + GS01,1, // GPI1 (GPWAKE) + GS02,1, // internal KBC PME + GS03,1, // V1 Interrupt + GS04,1, // EXTSMI# + GS05,1, // PME# + GS06,1, // INTRUDER# + GS07,1, // GP3 timer timeout + GS08,1, // ring + GS09,1, // mouse controller PME + GS10,1, // thermal detect (ebook) + GS11,1, // LID# + GS12,1, // battery low + GS13,1, // HDAC wakeup + GS14,1, // USB wakeup + GS15,1, // north module SERR# +} + +OperationRegion(GPIO, SystemIO, 0x0448, 0x4) +Field(GPIO, ByteAcc, NoLock, Preserve) { + ,7, + GPI7,1, // lid + ,1, + GPI9,1, // ebook + ,22, +} + +// PMIO_RX22/3 +OperationRegion(\GPSE, SystemIO, 0x0422, 0x2) // Genernal Purpose SCI Enable +Field(\GPSE, ByteAcc, NoLock, Preserve) { + GPS0, 1, // GPI0 SCI Enable + GPWK, 1, // GPI1 SCI Enable + KBCE, 1, // PS2 KB PME Enable + , 1, + EXTE, 1, // EXTSMI# Enable + PME, 1, // PCI PME Enable + , 2, + RING, 1, // Ring Wakeup + , 1, + THRM, 1, // Ebook/Thermal detect + LID, 1, // Lid Wakeup + , 1, // BATLOW Enable + HDA, 1, // HDA Enable + USBE, 1, // USB Resume + , 1, // NB SERR Detect +} + +// PMIO_RX28/9 +OperationRegion(\Glos, SystemIO, 0x0428, 0x2) // Global Status +Field(\Glos, ByteAcc, NoLock, Preserve) { + , 6, // + SSMI, 1, // software SMI + PRII, 1, // primary IRQ + , 2, // + SLPE, 1, // sleep enable(Rx05) + SIRS, 1, // serirq status + , 4, +} + +OperationRegion(\WIRQ, SystemIO, 0x042a, 0x1) // IRQ Resume Reg +Field(\WIRQ, ByteAcc, NoLock, Preserve) { + IRQR, 8, +} + +// from BIOS porting guide, section 13.2.2 +OperationRegion(\EDGE, SystemIO, 0x042c, 1) // SMI enable, lid edge polarity +Field(\EDGE, ByteAcc, NoLock, Preserve) { + , 1, // SMI enable (1 == enable) + , 1, // + PPOL, 1, // power button polarity (1 == falling) + , 1, // + , 1, // + , 1, // battery low enable (0 == enable) + TPOL, 1, // therm polarity (1 == falling) + LPOL, 1, // lid polarity (1 == falling) +} + +OperationRegion(\Stus, SystemIO, 0x0430, 0x1) // Global Status +Field(\Stus, ByteAcc, NoLock, Preserve) { + PADS, 8, +} + +OperationRegion(\Prie, SystemIO, 0x0434, 0x1) +Field(\Prie, ByteAcc, NoLock, Preserve) { + , 5, + CMAE, 1, // COMA_EN + CMBE, 1, // COMB_EN +} + +// +// General Purpose Event +// +Scope(\_GPE) +{ + Method(_L01) { + UPUT (0x31) // 1 + Notify(\_SB.PCI0.EC, 0x80) // GPWAKE, from the EC + } + + Method(_L02) { + UPUT (0x33) // 3 + Notify(\_SB.PCI0.VT86.PS2K, 0x02) //Internal Keyboard PME Status + } + + Method(_L04) { + UPUT (0x34) // 4 + Notify(\_SB.SLPB, 0x80) + } + + Method(_L05) { + UPUT (0x35) // 5 + Notify(\_SB.PCI0,0x2) + } + + Method(_L09) { + UPUT (0x39) // 9 + Notify(\_SB.PCI0.VT86.PS2M, 0x02) //Internal Mouse Controller PME Status + } + + Method(_L0A) { // EBOOK event (THRM#) + UPUT (0x65) // e + Not(TPOL, TPOL) // Flip the therm polarity bit + Store (One, GS10) // clear interrupt caused by polarity flip + Notify(\_SB.PCI0.EBK, 0x80) + } + + Method(_L0B) { // LID event + UPUT (0x66) // f + Store (GPI7, LPOL) // set edge detect from current lid state + Notify(\_SB.PCI0.LID, 0x80) + } + + Method(_L0D) { + Notify(\_SB.PCI0.HDAC, 0x02) + } + + Method(_L0E) { //USB Wake up Status + Notify(\_SB.PCI0.USB1, 0x02) + Notify(\_SB.PCI0.USB2, 0x02) + Notify(\_SB.PCI0.USB3, 0x02) + Notify(\_SB.PCI0.EHCI, 0x02) + } +} + +Name(PICF,0x00) // PIC or APIC? +Method(_PIC, 0x01, NotSerialized) { + Store (Arg0, PICF) +} + +// +// System Wake up +// +Method(_WAK, 1, Serialized) +{ +// FRTH(2) + Notify(\_SB.PCI0.USB1, 0x00) + Notify(\_SB.PCI0.USB2, 0x00) + Notify(\_SB.PCI0.USB3, 0x00) + Notify(\_SB.PCI0.EHCI, 0x00) + + Store(One, SCIZ) + + If (LEqual (Arg0, 1)) //S1 + { + Notify (\_SB.SLPB, 0x02) + } + + Or (Arg0, 0xA0, Local0) + Store (Local0, DBG1) //80 Port: A1, A2, A3.... + + IF (LEqual(Arg0, 0x01)) //S1 + { + And(IRQR,0x7F,IRQR) //Disable IRQ Resume Reg, IRQR:Rx2A + While(PRII){ //PRII:Rx28[7] + Store (One, PRII) //Clear Primary IRQ resume Status + } + While(LNotEqual(PADS, 0x00)) //PADS: Rx30[1:7] + { + Store (PADS, PADS) //Clear Primary Activity Detect Status + } + } + + Notify(\_SB.SLPB, 0x2) + + IF (LEqual(Arg0, 0x03)) //S3 + { + Store(0x2,\_SB.PCI0.MEMC.FSEG) //Set F Segment to Read only + // Notify(\_SB.PCI0, 0x00) + } + + Or (Arg0, 0xB0, Local0) + Store (Local0, DBG1) //80 Port: B1, B2, B3.... + + // always want to hear both lid events when awake + Store (GPI7, LPOL) // watch either edge + + // always want to hear ebook events (through THRM# GPIO) + Store (One, \_SB.PCI0.VT86.ENTH) + + Return (0) +} + +// +// System sleep down +// +Method (_PTS, 1, NotSerialized) +{ + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) //80 Port: F1, F2, F3.... + + // if (LIDX == 0), wake on rising edge only, else wake on either + Store (And(\_SB.PCI0.LID.LIDX, GPI7), LPOL) + + IF (LEqual(Arg0, 0x01)) // S1 + { + While(PRII) + { + Store (One, PRII) // Clear Primary IRQ resume Status + } + While(LNotEqual(PADS, 0x00)) + { + Store (PADS, PADS) // Clear Primary Activity Detect Status + } + Or(IRQR,0x80,IRQR) // Enable IRQ Resume Reg + + } //End of Arg0 EQ 0x01 + + IF (LEqual(Arg0, 0x03)) { // S3 + Store(0x0,\_SB.PCI0.MEMC.FSEG) // Disable F Segment Read/Write + } + + IF (LEqual(Arg0, 0x04)) { //S4 + } + + IF (LEqual(Arg0, 0x05)) { //S5 + Store (Zero, GS04) // Clear EXTSMI# Status, why? + } + Sleep(0x64) +// FRTH(One) + Return (0x00) +} + +// Method(STRC, 2) { // Compare two String +// If(LNotEqual(Sizeof(Arg0), Sizeof(Arg1))) { +// Return(1) +// } +// +// Add(Sizeof(Arg0), 1, Local0) +// +// Name(BUF0, Buffer(Local0) {}) +// Name(BUF1, Buffer(Local0) {}) +// +// Store(Arg0, BUF0) +// Store(Arg1, BUF1) +// +// While(Local0) { +// Decrement(Local0) +// If(LNotEqual(Derefof(Index(BUF0, Local0)), Derefof(Index(BUF1, Local0)))) { +// Return(1) +// } +// } +// Return(0) // Str1 & Str2 are match +// } + +// +// System Bus +// +Scope(\_SB) +{ + + Method(_INI, 0) + { + Store(One, SCIZ) + } + + Device (SLPB) + { + Name (_HID, EISAID("PNP0C0E")) // Hardware Device ID SLEEPBTN + Name (_STA, 0) // not present on XO. note that there are still + // Notify() calls to SLPB -- not sure what that will do. + Name(_PRW, Package(2){0x04,5}) //Internal Keyboard Controller PME Status; S5 + } + + Device(PCI0) + { +// Our WindowsXP SD build doesn't handle PCIe, so we have to claim basic PCI +// Name(_HID,EISAID ("PNP0A08")) // Indicates PCI Express host bridge hierarchy +// Name(_CID,EISAID ("PNP0A03")) // For legacy OS that doesn't understand the new HID + Name(_HID,EISAID ("PNP0A03")) // For legacy OS that doesn't understand the new HID + + Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0 + + Name (_BBN,0) + + Method(_INI, 0) + { + UPUT (0x4a) // J + } + + Name (_S3D, 3) + + Method(_STA, 0) { + Return(0x0F) // present, enabled, functioning + } + + Name(_PRW, Package(2){0x5,0x4}) // PME# + + Method(_CRS,0) { + Name(BUF0,ResourceTemplate() { + WORDBusNumber( // Bus 0 + ResourceConsumer, + MinNotFixed, + MaxNotFixed, + PosDecode, + 0x0000, + 0x0000, + 0x00FF, + 0x0000, + 0x0100 + ) + + IO( // IO Resource for PCI Bus + Decode16, + 0x0CF8, + 0x0CF8, + 1, + 8 + ) + + WORDIO( // IO from 0x0000 - 0x0cf7 + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0000, + 0x0CF7, + 0x0000, + 0x0CF8 + ) + + WORDIO( // IO from 0x0d00 - 0xffff + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0D00, + 0xFFFF, + 0x0000, + 0xF300 + ) + + DWORDMemory( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000A0000, + 0x000BFFFF, + 0x00000000, + 0x00020000 + ) + + DWORDMemory( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000C0000, + 0x000DFFFF, + 0x00000000, + 0x00020000 + ) + // XXX I don't know what this is + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, + 0xFED40000, + 0xFED44FFF, + 0x00000000, + 0x00005000, + ) + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min (calculated dynamically) + 0xBfffffff, // Max = 4GB - 1MB (fwh + fwh alias...) + 0x00000000, // Translation + 0x40000000, // Range Length (calculated dynamically) + , // Optional field left blank + , // Optional field left blank + MEM3 // Name declaration for this descriptor + ) + }) // end of BUF0 + + CreateDWordField(BUF0,MEM3._MIN, PMRN) + CreateDWordField(BUF0,MEM3._MAX, PMRM) + CreateDWordField(BUF0,MEM3._LEN, PMRL) + // XXX top of PCI memory space + Store(0xFFE80000, PMRM) + Store(\_SB.PCI0.MEMC.LTMA, Local0) + ShiftLeft(Local0, 16, PMRN) + Subtract (PMRM, PMRN, PMRL) + + Return(BUF0) + } // end of CRS + + Device(MEMC) { + Name(_ADR, 0x00000003) + + Method(_STA, 0) { + Return(0x0F) // present, enabled, functioning + } + + OperationRegion(MCPS,PCI_Config,0x00,0x100) + Field(MCPS,ByteAcc,NoLock,Preserve) + { + Offset(0x83), + , 4, + FSEG, 2, //Rx83[4:5] + , 2, + + Offset(0x84), + LTMA, 16, //Rx84 and Rx85. Low Top Address of Memory + + Offset(0x86), + , 2, + ENTS, 1, //Enable Top SMRAM Size + , 3, + TSMS, 2, // Top SMRAM Size + + Offset(0xA1), + , 4, + FBSZ, 3, // Frame Buffer Size + ENIG, 1, // Enable Internal Graphic + } + } + + // USBD Controller + Device (USBD) + { + Name(_ADR, 0x000B0000) + + OperationRegion(RUDC,PCI_Config,0x00,0x100) + Field(RUDC,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.USBD.VID, 0x1106)) { + Return(0x00) + } Else { + If(LEqual(\_SB.PCI0.USBD.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) // present, enabled, functioning + } + } + } + }//Device(USBD) + +// // SDIO Controller +// Device (SDIO) +// { +// Name(_ADR, 0x000C0000) +// +// OperationRegion(RSDC,PCI_Config,0x00,0x100) +// Field(RSDC,ByteAcc,NoLock,Preserve){ +// Offset(0x00), +// VID, 16, +// Offset(0x04), +// CMDR, 3, +// } +// +// Method(_STA, 0) +// { +// If(LNotEqual(\_SB.PCI0.SDIO.VID, 0x1106)) { +// Return(0x00) +// } Else { +// If(LEqual(\_SB.PCI0.SDIO.CMDR, 0x00)) { +// Return(0x0D) +// } Else { +// Return(0x0F) // present, enabled, functioning +// } +// } +// } +// }//Device(SDIO) + +// // SD $ MS Controller +// Device (SDMS) +// { +// Name(_ADR, 0x000D0000) +// +// OperationRegion(RSDM,PCI_Config,0x00,0x100) +// Field(RSDM,ByteAcc,NoLock,Preserve){ +// Offset(0x00), +// VID, 16, +// Offset(0x04), +// CMDR, 3, +// } +// +// Method(_STA, 0) +// { +// If(LNotEqual(\_SB.PCI0.SDMS.VID, 0x1106)) { +// Return(0x00) +// } Else { +// If(LEqual(\_SB.PCI0.SDMS.CMDR, 0x00)) { +// Return(0x0D) +// } Else { +// Return(0x0F) // present, enabled, functioning +// } +// } +// } +// }//Device(SDMS) +// +// // CE-ATA $ NF Controller(Card Boot) +// Device(CENF) +// { +// Name(_ADR, 0x000E0000) +// +// OperationRegion(RENF,PCI_Config,0x00,0x100) +// Field(RENF,ByteAcc,NoLock,Preserve){ +// Offset(0x00), +// VID, 16, +// Offset(0x04), +// CMDR, 3, +// } +// +// Method(_STA, 0) +// { +// If(LNotEqual(\_SB.PCI0.CENF.VID, 0x1106)) { +// Return(0x00) +// } Else { +// If(LEqual(\_SB.PCI0.CENF.CMDR, 0x00)) { +// Return(0x0D) +// } Else { +// Return(0x0F) // present, enabled, functioning +// } +// } +// } +// } +// +// Device(IDEC) +// { +// +// Name(_ADR, 0x000F0000) //D15F0: a Pata device +// +// Method(_STA,0,NotSerialized) //Status of the Pata Device +// { +// If(LNot(LEqual(\_SB.PCI0.IDEC.VID,0x1106))) +// { +// Return(0x00) //device not exists +// } +// Else +// { +// If(LEqual(\_SB.PCI0.IDEC.CMDR,0x00)) +// { +// Return(0x0D) //device exists & disable +// } +// Else +// { +// Return(0x0F) //device exists & enable +// } +// } +// } +// OperationRegion(SAPR,PCI_Config,0x00,0xC2) +// Field(SAPR,ByteAcc,NoLock,Preserve) +// { +// VID,16, +// Offset(0x04), +// CMDR,3, +// Offset(0x40), +// , 1, +// EPCH, 1, // Enable Primary channel. +// Offset(0x4A), +// PSPT, 8, // IDE Timings, Primary Slave +// PMPT, 8, // IDE Timings, Primary Master +// Offset(0x52), +// PSUT, 4, // Primary Slave UDMA Timing +// PSCT, 1, // Primary Drive Slave Cabal Type +// PSUE, 3, // Primary Slave UDMA Enable +// PMUT, 4, // Primary Master UDMA Timing +// PMCT, 1, // Primary Drive Master Cabal Type +// PMUE, 3, // Primary Master UDMA Enable +// } +// +// Name(REGF,0x01) //accessible OpRegion default +// Method(_REG,2,NotSerialized) // is PCI Config space accessible as OpRegion? +// { +// If(LEqual(Arg0,0x02)) +// { +// Store(Arg1,REGF) +// } +// } +// /* +// Name(TIM0,Package(0x04){ +// Package(){0x78,0xB4,0xF0,0x017F,0x0258}, +// Package(){0x20,0x22,0x33,0x47,0x5D}, +// Package(){0x78,0x50,0x3C,0x2D,0x1E,0x14,0x0F}, +// Package(){0x06,0x05,0x04,0x04,0x03,0x03,0x02,0x02,0x01,0x01,0x01,0x01,0x01,0x01,0x00} +// }) +// */ +// Name(TIM0, Package() +// { // Primary / Secondary channels timings +// Package(){120, 180, 240, 383, 600}, // Timings in ns - Mode 4,3,2,1,0 defined from ATA spec. +// Package(){0x20, 0x22, 0x33, 0x47, 0x5D }, // PIO Timing - Mode 4,3,2,1,0 +// Package(){4, 3, 2, 1, 0}, // PIO mode (TIM0,0) +// Package(){2, 1, 0, 0}, // Multi-word DMA mode +// Package(){120, 80, 60, 45, 30, 20, 15}, // Min UDMA Timings in ns +// Package(){6,5,4,4,3,3,2,2,1,1,1,1,1,1,0}, // UDMA mode +// Package(){0x0E, 8, 6, 4, 2, 1, 0}, // UDMA timing +// }) +// +// Name(TMD0,Buffer(0x14){}) +// CreateDwordField(TMD0,0x00,PIO0) +// CreateDwordField(TMD0,0x04,DMA0) +// CreateDwordField(TMD0,0x08,PIO1) +// CreateDwordField(TMD0,0x0C,DMA1) +// CreateDwordField(TMD0,0x10,CHNF) +// +// Name(GMPT, 0) // Master PIO Timings +// Name(GMUE, 0) // Master UDMA enable +// Name(GMUT, 0) // Master UDMA Timings +// Name(GSPT, 0) // Slave PIO Timings +// Name(GSUE, 0) // Slave UDMA enable +// Name(GSUT, 0) // Slave UDMA Timings +// +// Device(CHN0) //Primary Channel: Pata device +// { +// Name(_ADR,0x00) +// +// Method(_STA,0,NotSerialized) +// { +// If(LNotEqual(\_SB.PCI0.IDEC.EPCH, 0x1)) +// { +// Return(0x00) //channel disable +// } +// Else +// { +// Return(0x0F) //channel enable +// } +// } +// Method(_GTM,0,NotSerialized) //Get Timing Mode +// { +// Return(GTM(PMPT,PMUE,PMUT,PSPT,PSUE,PSUT)) +// } +// Method(_STM, 3) // Set Timing PIO/DMA Mode +// { +// Store(Arg0, TMD0) // Copy Arg0 into TMD0 buffer +// Store(PMPT, GMPT) // Master PIO Timings +// Store(PMUE, GMUE) // Master UDMA enable +// Store(PMUT, GMUT) // Master UDMA Timings +// Store(PSPT, GSPT) // Slave PIO Timings +// Store(PSUE, GSUE) // Slave UDMA enable +// Store(PSUT, GSUT) // Slave UDMA Timings +// STM() +// Store(GMPT, PMPT) // Master PIO Timings +// Store(GMUE, PMUE) // Master UDMA enable +// Store(GMUT, PMUT) // Master UDMA Timings +// Store(GSPT, PSPT) // Slave PIO Timings +// Store(GSUE, PSUE) // Slave UDMA enable +// Store(GSUT, PSUT) // Slave UDMA Timings +// } // end Method _STM +// +// Device(DRV0) //Master Device +// { +// Name(_ADR,0x00) //0 indicates master drive +// Method(_GTF,0,NotSerialized) //Get Task File: return a buffer of ATA command used to re-initialize //////the device +// { +// Return(GTF(0,PMUE,PMUT,PMPT)) +// } +// } +// Device(DRV1) //Slave Device +// { +// Name(_ADR,0x01) //1 indicates slave drive +// Method(_GTF,0,NotSerialized) //Get Task File: return a buffer of ATA command used to re-initialize //the device +// { +// Return(GTF(0,PSUE,PSUT,PSPT)) +// } +// } +// } +// +// Method(GTM,6,Serialized) +// { +// Store(Ones,PIO0) //default value: all bits set to 1 +// Store(Ones,PIO1) //default value: all bits set to 1 +// Store(Ones,DMA0) //default value: all bits set to 1 +// Store(Ones,DMA1) //default value: all bits set to 1 +// Store(0x10,CHNF) //default value: 0x10 +// If(REGF) +// { +// } +// Else +// { +// Return(TMD0) //unable to setup PCI config space as opRegion;return default value +// } +// Store(Match(DeRefOf(Index(TIM0,0x01)),MEQ,Arg0,MTR,0x00,0x00),Local6) +// If(LLess(Local6,Ones)) +// { +// Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x00)),Local6)),Local7) +// Store(Local7,DMA0) +// Store(Local7,PIO0) +// } +// Store(Match(DeRefOf(Index(TIM0,0x01)),MEQ,Arg3,MTR,0x00,0x00),Local6) +// If(LLess(Local6,Ones)) +// { +// Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x00)),Local6)),Local7) +// Store(Local7,DMA1) +// Store(Local7,PIO1) +// } +// If(Arg1) +// { +// Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x05)),Arg2)),Local5) +// Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x04)),Local5)),DMA0) +// Or(CHNF,0x01,CHNF) +// } +// If(Arg4) +// { +// Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x05)),Arg5)),Local5) +// Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x04)),Local5)),DMA1) +// Or(CHNF,0x04,CHNF) +// } +// Return(TMD0) //return timing mode +// } +// +// Method(STM, 0, Serialized) +// { +// +// If(REGF){} // PCI space not accessible +// Else { Return(TMD0) } +// +// Store(0x00, GMUE) // Master UDMA Disable +// Store(0x00, GSUE) // Slave UDMA Disable +// Store(0x07, GMUT) // Master UDMA Mode 0 +// Store(0x07, GSUT) // Slave UDMA Mode 0 +// +// If(And(CHNF, 0x1)) +// { +// Store(Match(DeRefOf(Index(TIM0, 4)), MLE, DMA0, MTR,0,0), Local0) // Get DMA mode +// Store(DeRefOf(Index(DeReFof(Index(TIM0, 6)), Local0)), GMUT) // Timing bit mask 66Mhz +// Or(GMUE, 0x07, GMUE) // Enable UltraDMA for Device 0 +// } +// Else // non - UDMA mode. Possible Multi word DMA +// { +// If(Or(LEqual(PIO0,Ones), LEqual(PIO0,0))) +// { +// If(And(LLess(DMA0,Ones), LGreater(DMA0,0))) +// { +// Store(DMA0, PIO0) // Make PIO0=DMA0 +// } +// } +// } +// +// If(And(CHNF, 0x4)) +// { +// Store(Match(DeRefOf(Index(TIM0, 4)), MLE, DMA1, MTR,0,0), Local0) +// Store(DeRefOf(Index(DeReFof(Index(TIM0, 6)), Local0)), GSUT) // Timing bit mask 66Mhz +// Or(GSUE, 0x07, GSUE) // Enable UltraDMA for Device 0 +// } +// Else // non - UDMA mode. Possible Multi word DMA +// { +// If(Or(LEqual(PIO1, Ones), LEqual(PIO1,0))) +// { +// If(And(LLess(DMA1, Ones), LGreater(DMA1,0))) +// { +// Store(DMA1, PIO1) // Make PIO1 = DMA1 +// } +// } +// } +// +// And(Match(DeRefOf(Index(TIM0, 0)), MGE, PIO0, MTR,0,0), 0x3, Local0) +// Store(DeRefOf(Index(DeReFof(Index(TIM0, 1)), Local0)), Local1) +// Store(Local1, GMPT) +// +// And(Match(DeRefOf(Index(TIM0, 0)), MGE, PIO1, MTR,0,0), 0x3, Local0) +// Store(DeRefOf(Index(DeReFof(Index(TIM0, 1)), Local0)), Local1) +// Store(Local1, GSPT) +// Return(TMD0) +// } // end Method STM +// +// Method(GTF , 4 , Serialized) +// { +// Store(Buffer(7){0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF}, Local1) +// Store(Buffer(7){0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF}, Local2) +// CreateByteField(Local1, 1, Mode) // PIO mode +// CreateByteField(Local2, 1, UMOD) // Ultra mode +// CreateByteField(Local1, 5, PCHA) // master or slave +// CreateByteField(Local2, 5, UCHA) // master or slave +// And(Arg0,0x03,Local3) +// +// If(Lequal(And(Local3,0x01),0x01)) +// { +// Store(0xB0,PCHA) // drive 1 +// Store(0xB0,UCHA) // drive 1 +// } +// +// If(Arg1) +// { +// Store(DeRefOf(Index(DeReFof(Index(TIM0, 5)), Arg2)), UMOD) //Programming DMA Mode +// Or( UMOD, 0x40, UMOD) +// } +// Else +// { // non-UltraDMA +// Store(Match(DeRefOf(Index(TIM0, 1)), MEQ, Arg3, MTR,0,0), Local0) +// Or(0x20, DeRefOf(Index(DeReFof(Index(TIM0, 3)), Local0)), UMOD) +// } +// +// Store(Match(DeRefOf(Index(TIM0, 1)), MEQ, Arg3, MTR,0,0), Local0) +// Or(0x08, DeRefOf(Index(DeReFof(Index(TIM0, 2)), Local0)), Mode) +// Concatenate(Local1, Local2, Local6) +// Return(Local6) +// +// } // end of GTF +// } + + Device(USB1) { + Name(_ADR,0x00100000) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F0,PCI_Config,0x00,0xC2) + Field(U2F0,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U3IR, 4, //USB1 Interrupt Line + Offset(0x84), + ECDX, 2 //USB1 PM capability status register + } + + Method(_STA,0) { //Status of the USB1 Device + If(LEqual(\_SB.PCI0.USB1.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } + } + + Device(USB2) { + Name(_ADR,0x00100001) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F1,PCI_Config,0x00,0xC2) + Field(U2F1,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U4IR, 4, //USB2 Interrupt Line + Offset(0x84), + ECDX, 2 //USB2 PM capability status register + } + + Method(_STA,0) { //Status of the USB2 Device + If(LEqual(\_SB.PCI0.USB2.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } + } + + Device(USB3) { + Name(_ADR,0x00100002) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F2,PCI_Config,0x00,0xC2) + Field(U2F2,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U5IR, 4, //USB3 Interrupt Line + Offset(0x84), + ECDX, 2 //USB3 PM capability status register + } + + Method(_STA,0) { //Status of the USB3 Device + If(LEqual(\_SB.PCI0.USB3.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } + } + + Device(EHCI) { + Name(_ADR,0x00100004) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F4,PCI_Config,0x00,0xC2) + Field(U2F4,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U7IR, 4, //EHCI1 Interrupt Line + Offset(0x84), + ECDX, 2 //EHCI1 PM capability status register + } + + Method(_STA,0) { //Status of the EHCI1 Device + If(LEqual(\_SB.PCI0.EHCI.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } + } + + Device (PEXX) + { + Name (_HID, EISAID ("PNP0C01")) + Name (_STA, 0x0F) + Name (_CRS, + ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0xE0000000, 0x10000000) + } + ) + } + + Device(VT86) + { + Name(_ADR,0x00110000) //Address+function. + + OperationRegion(VTSB, PCI_Config, 0x00, 0x100) + Field(\_SB.PCI0.VT86.VTSB,ByteAcc,NoLock,Preserve) { + Offset(0x2), + DEID, 16, // Device ID + + Offset(0x2C), + ID2C,8, // RX2C + ID2D,8, // RX2D + ID2E,8, // RX2E + ID2F,8, // RX2F + + Offset(0x44), + PIRE, 4, + PIRF, 4, + PIRG, 4, + PIRH, 4, // PIRQH# Routing + + Offset(0x46), + POLE, 1, // INTE polarity + POLF, 1, // INTF polarity + POLG, 1, // INTG polarity + POLH, 1, // INTH polarity + ENR8, 1, // enable INTE~H routing by Rx44~Rx45. + , 1, + ECOM, 1, + + Offset(0x4E), + , 3, + EP74, 1, // Enable 74/75 Access CMOS + , 4, + + Offset(0x50), + , 1, + ESB3, 1, // RX5001 EHCI1 + ESB2, 1, // RX5002 USB3 + EIDE, 1, // RX5003 EIDE + EUSB, 1, // RX5004 USB1 + ESB1, 1, // RX5005 USB2 + USBD, 1, // RX5006 USB Device Mode controller + + Offset(0x51), + EKBC, 1, // RX5100 Internal Keyboard controller + KBCC, 1, // RX5101 Internal KBC Configuration + EPS2, 1, // RX5102 Internal PS2 Mouse + ERTC, 1, // RX5103 Internal RTC + SDIO, 1, // RX5104 enable SDIO controller + , 2, + + Offset(0x55), + , 4, + PIRA, 4, // PCI IRQA + PIRB, 4, // PCI IRQB + PIRC, 4, // PCI IRQC + , 4, + PIRD, 4, // PCI IRQD + + Offset(0x58), + , 6, + ESIA, 1, // Enable Source Bridge IO APIC + , 1, + + Offset(0x81), // Enable ACPI I/O + , 7, + ENIO, 1, + + Offset(0x88), + , 7, + IOBA, 9, // Power Management I/O Base + + Offset(0x8c), // Host Power Management Control + , 3, + ENTH, 1, // THRM# enable + + Offset(0x94), + , 5, + PLLD, 1, // RX9405 Internal PLL Reset During Suspend 0:Enable,1:Disable + + Offset(0xB0), + , 4, + EU1E, 1, // Embedded COM1 + EU2E, 1, // Embedded COM2 + , 2, + + Offset(0xB2), + UIQ1, 4, // UART1 IRQ + UIQ2, 4, // UART2 IRQ + + Offset(0xB4), + U1BA, 7, // UART1 I/O base address. + , 1, + U2BA, 7, // UART2 I/O base address. + , 1, + + Offset(0xB7), + , 3, + UDFE, 1, // UART DMA Funtion Enable + + Offset(0xB8), + , 2, + DIBA, 14, // UART DMA I/O Base Address + + Offset(0xBC), + SPIB, 24, + + Offset(0xD0), + , 4, + SMBA, 12, // SMBus I/O Base (16-byte I/O space) + + Offset(0xD2), + ENSM, 1, // Enable SMBus IO + , 7, + + Offset(0xF6), + REBD, 8, //Internal Revision ID + } + + Device(APCM) // APIC MMIO + { + Name(_HID, EISAID("PNP0C02")) // Hardware Device ID, Motherboard Resources + Name(_UID, 0x1100) + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed(ReadWrite, 0xFEC00000, 0x00001000) // IO APIC + }) + } + + Device(PS2M) //PS2 Mouse + { + Name(_HID,EISAID("PNP0F13")) + Name(_STA, 0xF) // not present: not used on XO + Name(_CRS, ResourceTemplate () { IRQNoFlags () {12} }) + Name(_PRW, Package() {0x09, 0x04}) + } + + Device(PS2K) // PS2 Keyboard + { + Name(_HID,EISAID("PNP0303")) + Name(_CID,EISAID("PNP030B")) // Microsoft reserved PNP ID + + Name(_STA,0xF) // not present: not used on XO + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01, ) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01, ) + IRQNoFlags () {1} + }) + Name(_PRW, Package() {0x02, 0x04}) + } + + Device(DMAC) + { + Name(_HID, EISAID("PNP0200")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16, 0x00, 0x00, 0, 0x10) // Master DMA Controller + IO(Decode16, 0x81, 0x81, 0, 0x03) // DMA Page Registers + IO(Decode16, 0x87, 0x87, 0, 0x01) + IO(Decode16, 0x89, 0x89, 0, 0x03) + IO(Decode16, 0x8F, 0x8F, 0, 0x01) + IO(Decode16, 0xC0, 0xC0, 0, 0x20) // Slave DMA Controller + DMA(Compatibility,NotBusMaster,Transfer8) {4} // Cascade channel + }) + } + + Device(RTC) + { + Name(_HID,EISAID("PNP0B00")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16, 0x70, 0x70, 0x00, 0x02) + IO(Decode16, 0x74, 0x74, 0x00, 0x02) + IRQNoFlags() {8} + }) + } + + Device(PIC) + { + Name(_HID,EISAID("PNP0000")) + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x20,0x20,0x00,0x02) + IO(Decode16,0xA0,0xA0,0x00,0x02) + }) + } + + Device(FPU) + { + Name(_HID,EISAID("PNP0C04")) + Name(_CRS,ResourceTemplate() { + IO(Decode16,0xF0,0xF0,0x00,0x1) + IRQNoFlags(){13} + }) + } + + Device(TMR) + { + Name(_HID,EISAID("PNP0100")) + + Name(_CRS, ResourceTemplate() + { + IO(Decode16,0x40,0x40,0x00,0x04) + IRQNoFlags() {0} + }) + } + + Device(SPKR) // System Speaker + { + Name(_HID,EISAID("PNP0800")) + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x61,0x61,0x01,0x01) + }) + } + + Name (ICRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) // The flags is the value of Byte 3 of IRQ Description Definition + { } // The value decides the value of Byte 1 and byte 2 of IRQ Description Definition + }) + + Name(PRSA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} + }) + + Device(LNKA) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 1) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRA, 0x00)) + { + Return(0x09) // disabled + } Else { + Return(0x0B) // enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRA) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRA, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) // Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRA) + } + } + + Device(LNKB) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 2) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRB, 0x00)) + { + Return(0x09) // disabled + } Else { + Return(0x0B) // enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRB) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRB, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) // Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRB) + } + } + + + Device(LNKC) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 3) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRC, 0x00)) + { + Return(0x09) // disabled + } Else { + Return(0x0B) // enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRC) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRC, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRC) + } + } + + Device(LNKD) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 4) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRD, 0x00)) + { + Return(0x09) // disabled + } Else { + Return(0x0B) // enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRD) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRD, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRD) + } + } + + Device(LNKE) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 5) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRE, 0x00)) + { + Return(0x09) // disabled + } Else { + Return(0x0B) // enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRE) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRE, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRE) + Store(One,ENR8) + Store(Zero,POLE) + } + } + + Device(LNKF) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 6) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRF, 0x00)) + { + Return(0x09) // disabled + } Else { + Return(0x0B) // enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRF) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRF, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRF) + Store(One,ENR8) + Store(Zero,POLF) + } + } + + Device(LNK0) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 7) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRG, 0x00)) + { + Return(0x09) // disabled + } Else { + Return(0x0B) // enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRG) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRG, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRG) + Store(One,ENR8) + Store(Zero,POLG) + } + } + + Device(LNK1) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 8) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRH, 0x00)) + { + Return(0x09) // disabled + } Else { + Return(0x0B) // enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRH) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRH, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRH) + Store(One,ENR8) + Store(Zero,POLH) + } + } + + Mutex (MUEC, 0x00) + OperationRegion (ECCP, SystemIO, 0x068, 0x05) + + // NB -- the EC routines all return 0 for failure + + Field (ECCP, ByteAcc, NoLock, Preserve) + { + ECDA, 8, // 0x68 + , 8, + , 8, + , 8, + ECCM, 8, // 0x6c + } + + // force clear OBF by reading/discarding 0x68 + Method (OBFZ, 0, Serialized) + { + Store (100, Local0) + While (LAnd (Decrement (Local0), And (ECCM, 1))) + { + Store (ECDA, Local1) + Sleep(1) + } + Return (LNotEqual (Local0, Zero)) + } + + // wait for IBF == 0 + Method (IBFZ, 0, Serialized) + { + Store (100, Local0) + While (LAnd (Decrement (Local0), And (ECCM, 2))) + { + Sleep(1) + } + Return (LNotEqual (Local0, Zero)) + } + + // wait for IBF == 1 + Method (IBFN, 0, Serialized) + { + Store (100, Local0) + While (LAnd (Decrement (Local0), LNot (And (ECCM, 2)))) + { + Sleep(1) + } + Return (LNotEqual (Local0, Zero)) + } + + // wait for OBF == 1 + Method (OBFN, 0, Serialized) + { + Store (100, Local0) + While (LAnd (Decrement (Local0), LNot (And (ECCM, 1)))) + { + // UPUT (0x38) + // UDOT (ECCM) + Sleep(1) + } + Return (LNotEqual (Local0, Zero)) + } + + // EC read byte helper + Method (ECRB, 0, NotSerialized) + { + if (OBFN ()) { Return(ECDA) } + Return (Ones) + } + + // EC command helper + Method (ECWC, 1, NotSerialized) + { + UPUT (0x21) // ! + UDOT (Arg0) + if (OBFZ ()) { + // UPUT (0x35) + if (IBFZ ()) { + // UPUT (0x36) + Store (Arg0, ECCM) // write the command to 0x6c + if (IBFZ ()) { + // UPUT (0x37) + Return (One) + } + } + } + Return(Zero) + } + + // EC command (zero args) + Method (ECW0, 2, NotSerialized) + { + If (Acquire (MUEC, 0xFFFF)) { Return (One) } + + if (ECWC (Arg0)) { + Release(MUEC) + Return(One) + } + UPUT (0x2a) // * + Release(MUEC) + Return (Zero) + } + + // EC command - 1 arg + Method (ECW1, 2, NotSerialized) + { + If (Acquire (MUEC, 0xFFFF)) { Return (One) } + + if (ECWC (Arg0)) { + if (IBFZ ()) { + UPUT (0x2b) // + + UDOT (Arg1) + Store (Arg1, ECDA) // write the data to 0x68 + Release(MUEC) + Return(One) + } + } + UPUT (0x2a) // * + Release(MUEC) + Return (Zero) + } + + // EC command - 2 args + Method (ECW2, 3, NotSerialized) + { + If (Acquire (MUEC, 0xFFFF)) { Return (One) } + + if (ECWC (Arg0)) { + if (IBFZ ()) { + UPUT (0x2b) // + + UDOT (Arg1) + Store (Arg1, ECDA) // write the data to 0x68 + if (IBFZ ()) { + UPUT (0x2b) // + + UDOT (Arg2) + Store (Arg2, ECDA) // write the next data to 0x68 + Release(MUEC) + Return(One) + } + } + } + UPUT (0x2a) // * + Release(MUEC) + Return (Zero) + } + + // EC command - no arg, 1 return byte + Method (ECR1, 1, NotSerialized) + { + + If (Acquire (MUEC, 0xFFFF)) { Return (One) } + // UPUT (0x4c) // L + + If (ECWC (Arg0)) { + // UPUT (0x31) + Store (10, Local0) // Ten retries + While (Decrement(Local0)) { + // UPUT (0x32) + Store (ECRB (), Local1) + If (LNotEqual (Local1, Ones)) + { + UPUT (0x3d) // = + UDOT (Local1) + Release(MUEC) + Return (Local1) // Success + } + UPUT (0x2c) // , + } + } + UPUT (0x2a) // * + Release(MUEC) + Return (Ones) + } + + // EC command - one arg, one return byte + Method (ECWR, 2, NotSerialized) + { + Store (10, Local0) // Ten retries + + If (Acquire (MUEC, 0xFFFF)) { Return (One) } + + If (ECWC (Arg0)) { + if (IBFZ ()) { + UPUT (0x2b) // + + UDOT (Arg1) + Store (Arg1, ECDA) // write the data to 0x68 + While (Decrement(Local0)) { + Store (ECRB (), Local1) + If (LNotEqual (Local1, Ones)) + { + UPUT (0x3d) // = + UDOT (Local1) + Release(MUEC) + Return (Local1) // Success + } + UPUT (0x2c) // , + } + } + } + UPUT (0x2a) // * + Release(MUEC) + Return (Ones) + } + + Mutex (ACMX, 0x00) + + Device (AC) { /* AC adapter */ + Name (_HID, "ACPI0003") + Name (_PCL, Package (0x01) { _SB }) // Power consumer list - points to main system bus + + Method (_PSR, 0, NotSerialized) + { + If (LNot (Acquire (ACMX, 5000))) + { + UPUT (0x70) // p + // Store (ECRD (0xFA40), Local0) + Store (ECR1 (0x15), Local0) // CMD_READ_BATTERY_STATUS + Release (ACMX) + } + + // If (And (Local0, One)) + If (And (Local0, 0x10)) + { + Return (One) + } Else { + Return (Zero) + } + } + + Name (_STA, 0x0F) + } + + Name (BIFP, Package (0x0D) // Battery info (static) p 342 + { + One, // Power units - 1 : mAh / mA + 0x0ED8, // Design capacity + 0x0BB8, // Last Full Charge capacity + One, // rechargable + 0x1770, // Full voltage in mV + 0x01C2, // warning capacity + 0x0F, // low capacity + 0x01B3, // granularity between low and warning + 0x09F6, // granularity between warning and full + "NiMH (GP) ", // Model number + "", // serial number + "NiMH", // type + "OLPC " // OEM info + }) + + Name (BSTP, Package (0x04) // Battery status (dynamic) p 343 + { + Zero, // state - bitmask 1: discharging 2: charging 4: critical + 760, // current flow + 2910, // remaining capacity + 23306 // voltage in mV + }) + + Device (BATT) { + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, One) + Name (_PCL, Package (0x01) + { + _SB + }) + + Method (_STA, 0, NotSerialized) // Battery Status + { + + If (LNot (Acquire (ACMX, 5000))) + { + UPUT (0x73) // s + // Store (ECRD (0xFAA4), Local0) + Store (ECR1 (0x15), Local0) // CMD_READ_BATTERY_STATUS + Release (ACMX) + } + + If (And (Local0, One)) // ECRD(0xfaa4) & 0x01 => Battery inserted + { + Return (0x1F) + } Else { + Return (0x0F) + } + } + + Method (_BIF, 0, NotSerialized) // Battery Info + { + If (LNot (Acquire (ACMX, 5000))) + { + // Store (ECRD (0xFB5F), Local0) + Store (ECR1 (0x2c), Local0) // CMD_READ_BATTERY_TYPE + // Store (ECRD (0xF929), Local1) // FIXME -- BAT_SOC_WARNNING + Store (15, Local1) // EC hard-codes this (BAT_SOC_WARNNING) + Switch (Local0) + { + Case (0x11) + { + UPUT (0x42) // B + Store (3800, Index (BIFP, One)) + Store (3000, Index (BIFP, 2)) + Store (6000, Index (BIFP, 0x04)) + Multiply (Local1, 30, Local1) + Store (Local1, Index (BIFP, 5)) + Store (15, Index (BIFP, 6)) + Store (Subtract (Local1, 15), Index (BIFP, 7)) + Store (Subtract (3000, Local1), Index (BIFP, 8)) + Store ("NiMH (GP) ", Index (BIFP, 9)) + Store ("", Index (BIFP, 10)) + Store ("NiMH", Index (BIFP, 11)) + Store ("GoldPeak ", Index (BIFP, 0x0C)) + UPUT (0x62) // b + } + Case (0x12) + { + UPUT (0x44) // D + Store (3000, Index (BIFP, One)) + Store (2800, Index (BIFP, 2)) + Store (6000, Index (BIFP, 4)) + Multiply (Local1, 28, Local1) + Store (Local1, Index (BIFP, 5)) + Store (14, Index (BIFP, 6)) + Store (Subtract (Local1, 14), Index (BIFP, 7)) + Store (Subtract (2800, Local1), Index (BIFP, 8)) + Store ("LiFePO4 (GP) ", Index (BIFP, 9)) + Store ("", Index (BIFP, 10)) + Store ("LiFePO4", Index (BIFP, 11)) + Store ("GoldPeak ", Index (BIFP, 0x0C)) + UPUT (0x64) // d + } + Case (0x22) + { + UPUT (0x43) // C + Store (3550, Index (BIFP, One)) + Store (3100, Index (BIFP, 2)) + Store (6500, Index (BIFP, 4)) + Multiply (Local1, 31, Local1) + Store (Local1, Index (BIFP, 5)) + Store (15, Index (BIFP, 6)) + Store (Subtract (Local1, 15), Index (BIFP, 7)) + Store (Subtract (3100, Local1), Index (BIFP, 8)) + Store ("LiFePO4 (BYD) ", Index (BIFP, 9)) + Store ("", Index (BIFP, 10)) + Store ("LiFePO4", Index (BIFP, 11)) + Store ("BYD ", Index (BIFP, 0x0C)) + UPUT (0x63) // c + } + } + UPUT (0x49) // I + + Release (ACMX) + } + + Return (BIFP) + } + + Method (_BST, 0, NotSerialized) + { + If (LNot (Acquire (ACMX, 5000))) + { + UPUT (0x74) // t + // If (And (ECRD (0xFAA5), One)) + Store (ECR1(0x15), Local0) // CMD_READ_BATTERY_STATUS + If (And (Local0, 0x20)) + { + Store (0x02, Local1) // charging + } + ElseIf (And (Local0, 0x40)) // + { + Store (One, Local1) // discharging + } + + Sleep (15) + // Store (ECRD (0xF910), Local0) + Store (ECR1 (0x16), Local0) // CMD_READ_SOC + If (LLess (Local0, 15)) + { + Or (Local1, 4, Local1) // critical + } + + Store (Local1, Index (BSTP, Zero)) + Sleep (15) + + // Switch (ECRD (0xFB5F)) + Switch (ECR1 (0x2c)) // CMD_READ_BATTERY_TYPE + { + Case (0x11) + { + Store (760, Index (BSTP, One)) + Multiply (Local0, 30, Local2) + } + Case (0x22) + { + Store (1500, Index (BSTP, One)) + Multiply (Local0, 31, Local2) + } + Case (0x12) + { + Store (1500, Index (BSTP, One)) + Multiply (Local0, 28, Local2) + } + } + + Store (Local2, Index (BSTP, 2)) + Release (ACMX) + } + + Return (BSTP) + } + } + + Device(HPET) { + Name(_HID,EISAID("PNP0103")) + Name(_UID, 0) + Name(_CRS,ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xfed00000, 0x00000400, MEM0) + }) + } + + Device(RMSC) { // all "PNP0C02" devices- pieces that don't fit anywhere else + Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices + Name (_UID, 0x13) + + Name(CRS,ResourceTemplate(){ + + IO(Decode16,0x10,0x10,0x00,0x10) + IO(Decode16,0x22,0x22,0x00,0x1E) + IO(Decode16,0x44,0x44,0x00,0x1C) + IO(Decode16,0x62,0x62,0x00,0x02) + IO(Decode16,0x65,0x65,0x00,0x0B) + IO(Decode16,0x72,0x72,0x00,0x02) + IO(Decode16,0x76,0x76,0x00,0x09) + IO(Decode16,0x80,0x80,0x00,0x01) + IO(Decode16,0x84,0x84,0x00,0x03) + IO(Decode16,0x88,0x88,0x00,0x01) + IO(Decode16,0x8c,0x8c,0x00,0x03) + IO(Decode16,0x90,0x90,0x00,0x02) + IO(Decode16,0x92,0x92,0x00,0x01) // INIT & Fast A20 port + IO(Decode16,0x93,0x93,0x00,0x0C) + IO(Decode16,0xA2,0xA2,0x00,0x1E) + IO(Decode16,0xE0,0xE0,0x00,0x10) + IO(Decode16,0x380,0x380,0x00,0x8) // Additional EC port + IO(Decode16,0x3E0,0x3E0,0x00,0x8) + IO(Decode16,0x3F8,0x3F8,0x00,0x8) // UART + + // Reserve 4D0 and 4D1 for IRQ edge/level control port + IO(Decode16, 0x4D0,0x4D0,0x00,0x2) + // ACPI IO base address allocation + IO(Decode16, 0, 0, 0, 0, IO0) + // SMBus I/O space if applicable + IO(Decode16, 0, 0, 0, 0, IO1) + // SPI Memory Map IO Base + Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, MEM0) + Memory32Fixed(ReadWrite, 0xfed30000, 0x00001000) // SPI MMIO + }) + + Method(_CRS, 0) + { + If(LEqual(\_SB.PCI0.VT86.ENIO, 0x01)) // If we should privide the DSDT, ACPI IO must be enabled. + { + CreateWordField(CRS, ^IO0._MIN, MIN0) + CreateWordField(CRS, ^IO0._MAX, MAX0) + CreateByteField(CRS, ^IO0._LEN, LEN0) + Store(\_SB.PCI0.VT86.IOBA, Local0) + ShiftLeft(Local0, 7, Local0) + Store(Local0, MIN0) + Store(Local0, MAX0) + Store(0x80, LEN0) + } + + If(LEqual(\_SB.PCI0.VT86.ENSM, 0x01)) + { + CreateWordField(CRS, ^IO1._MIN, MIN1) + CreateWordField(CRS, ^IO1._MAX, MAX1) + CreateByteField(CRS, ^IO1._LEN, LEN1) + Store(\_SB.PCI0.VT86.SMBA, Local0) + ShiftLeft(Local0, 4, Local0) + Store(Local0, MIN1) + Store(Local0, MAX1) + Store(0x10, LEN1) // Length: 16 Byte + } + + If(LNotEqual(\_SB.PCI0.VT86.SPIB, 0x00)) + { + CreateDWordField(CRS, ^MEM0._BAS, BAS2) + CreateDWordField(CRS, ^MEM0._LEN, LEN2) + Store(\_SB.PCI0.VT86.SPIB, Local0) + ShiftLeft(Local0, 8, Local0) + Store(Local0, BAS2) + Store(0x100, LEN2) + } + + Return(CRS) + } + } + + } // End of (VT86) + + Name(PICM, Package(){ + // VIA VGA Device(Integrated Graphics Device) + Package(){0x0001ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // VGA, INTA + + //PCI Slot 1 + Package(){0x0008ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTA + Package(){0x0008ffff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTB + Package(){0x0008ffff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTC + Package(){0x0008ffff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTD + + //PCI Slot 2 + Package(){0x0009ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTA + Package(){0x0009ffff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTB + Package(){0x0009ffff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTC + Package(){0x0009ffff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTD + + //PCI Slot 3 + Package(){0x000Affff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTA + Package(){0x000Affff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTB + Package(){0x000Affff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTC + Package(){0x000Affff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTD + + // USB Device Controller + Package(){0x000Bffff, 0, \_SB.PCI0.VT86.LNKA, 0}, + + // SDIO Controller + Package(){0x000cffff, 0, \_SB.PCI0.VT86.LNKA, 0}, + // SD $ MS Controller + Package(){0x000dffff, 0, \_SB.PCI0.VT86.LNKB, 0}, + // CE-ATA $ NF Controller(Card Boot) + Package(){0x000effff, 0, \_SB.PCI0.VT86.LNKC, 0}, + // VIA VX800 IDE + Package(){0x000fffff, 0, \_SB.PCI0.VT86.LNKB, 0}, + + // VIA UHCI USB1 Device + Package(){0x0010ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, + // VIA UHCI USB2 Device + Package(){0x0010ffff, 1, \_SB.PCI0.VT86.LNKB, 0}, + // VIA UHCI USB3 Device + Package(){0x0010ffff, 2, \_SB.PCI0.VT86.LNKC, 0}, + // VIA EHCI USB 2.0 Device + Package(){0x0010ffff, 3, \_SB.PCI0.VT86.LNKD, 0}, + + // SB HDAC(Azalia) Audio + Package(){0x0014ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // HD Audio, INTA + }) + + Name(APIC, Package(){ + // VIA VGA Device(Integrated Graphics Device) + Package(){0x0001ffff, 0, 0, 0x10}, + + //PCI Slot 1 + Package(){0x0008ffff, 0, 0, 0x10}, + Package(){0x0008ffff, 1, 0, 0x10}, + Package(){0x0008ffff, 2, 0, 0x10}, + Package(){0x0008ffff, 3, 0, 0x10}, + + //PCI Slot 2 + Package(){0x0009ffff, 0, 0, 0x10}, + Package(){0x0009ffff, 1, 0, 0x10}, + Package(){0x0009ffff, 2, 0, 0x10}, + Package(){0x0009ffff, 3, 0, 0x10}, + + //PCI Slot 3 + Package(){0x000Affff, 0, 0, 0x10}, + Package(){0x000Affff, 1, 0, 0x10}, + Package(){0x000Affff, 2, 0, 0x10}, + Package(){0x000Affff, 3, 0, 0x10}, + + // USB Device Controller + Package(){0x000Bffff, 0, 0, 0x13}, // USBD, INTA + + // SDIO Controller + Package(){0x000cffff, 0, 0, 0x16}, // SDIO, INTA + // SD $ MS Controller + Package(){0x000dffff, 0, 0, 0x17}, // Card Reader, INTA + // CE-ATA $ NF Controller(Card Boot) + Package(){0x000effff, 0, 0, 0x14}, // Card Boot(NAND Flash), INTA + // VIA VX800 IDE + Package(){0x000fffff, 0, 0, 0x15}, //IDE, INTA + + // VIA UHCI USB1 Device + Package(){0x0010ffff, 0, 0, 0x14}, + // VIA UHCI USB2 Device + Package(){0x0010ffff, 1, 0, 0x16}, + // VIA UHCI USB3 Device + Package(){0x0010ffff, 2, 0, 0x15}, + // VIA EHCI USB 2.0 Device + Package(){0x0010ffff, 3, 0, 0x17}, + + // SB HDAC(Azalia) Audio + Package(){0x0014ffff, 0, 0, 0x11}, //HD Audio , INTA + + }) // end of APIX + + Method(_PRT, 0, NotSerialized) + { + If(LNot(PICF)) + { + //PIC + Return(PICM) + } Else { + //APIC + Return(APIC) + } + } + + Device(P2PB) + { + Name (_ADR, 0x00130000) + + OperationRegion(RP2P,PCI_Config,0x00,0x100) + Field(RP2P,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x19), + BUS1, 8, + } + + Method(_BBN,0) + { + Return(BUS1) + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.P2PB.VID, 0x1106)) { + Return(0x00) + } Else { + If(LEqual(\_SB.PCI0.P2PB.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) // present, enabled, functioning + } + } + } + + Name(PIC4, Package(){ + Package(){0x0003ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, + + Package(){0x0004ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, + + Package(){0x0005ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, + }) + + Name(API4, Package(){ + Package(){0x0003ffff, 0, 0, 0x10}, + Package(){0x0003ffff, 1, 0, 0x10}, + Package(){0x0003ffff, 2, 0, 0x10}, + Package(){0x0003ffff, 3, 0, 0x10}, + + Package(){0x0004ffff, 0, 0, 0x10}, + Package(){0x0004ffff, 1, 0, 0x10}, + Package(){0x0004ffff, 2, 0, 0x10}, + Package(){0x0004ffff, 3, 0, 0x10}, + + Package(){0x0005ffff, 0, 0, 0x10}, + Package(){0x0005ffff, 1, 0, 0x10}, + Package(){0x0005ffff, 2, 0, 0x10}, + Package(){0x0005ffff, 3, 0, 0x10}, + }) + + Method(_PRT, 0x0, NotSerialized) + { + If(LNot(PICF)) + { + Return(PIC4) + } Else { + Return(API4) + } + } + + Method(_PRW, 0x00, NotSerialized) + { + Return(Package(){0x05,4}) //PME# + } + Device(P4D3) + { + Name(_ADR, 0x00030000) + } + } // Device(P2PB) + + Device (EC) { + Name (_HID, "XO15EC") + Name (_PRW, Package (0x02) { 0x01, 0x04 }) // Event 01, wakes from S4 + Name (_GPE, 0x01) + + Method(_INI, 0) + { + UPUT (0x49) // I + } + + } // Device(EC) + + Device (EBK) { + Name (_HID, "XO15EBK") + Name (_PRW, Package (0x02) { 0x0A, 0x04 }) // Event 0A, wakes from S4 + + Method(_INI, 0) + { + Store (One, \_SB.PCI0.VT86.ENTH) + Store (One, THRM) + Store (GPI9, TPOL) // init edge detect from current state + } + + Method(EBK) { + If (GPI9) { // non-zero --> switch is open + UPUT (0x65) // e + } Else { + UPUT (0x45) // E + } + If (LNotEqual(GPI9, TPOL)) { + Store (GPI9, TPOL) // (re)init edge detect + } + Return(GPI9) + } + } // Device(EBK) + + Device (LID) { + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package (0x02) { 0x0B, 0x04 }) // Event 0B, wakes from S4 + + // set to 1 to enable LID wakeups on both open/close + Name (LIDX, 0) + + Method(_INI, 0) + { + Store (GPI7, LPOL) // init edge detect from current state + } + + Method(_LID) { + If (GPI7) { // non-zero --> switch (and lid) is open + UPUT (0x6c) // l + } Else { + UPUT (0x4c) // L + } + + If (LNotEqual(GPI7, LPOL)) { + Store (GPI7, LPOL) // (re)init edge detect + } + + Return(GPI7) + } + + Method (LIDW, 1) + { + Store (Arg0, LIDX) + } + + } // Device(LID) + + Device(HDAC) + { + Name(_ADR, 0x00140000) + + OperationRegion(RHDA,PCI_Config,0x00,0x100) + Field(RHDA,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.HDAC.VID, 0x1106)) { + Return(0x00) + } Else { + If(LEqual(\_SB.PCI0.HDAC.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) // present, enabled, functioning + } + } + } + + Method(_PRW) + { + Return (Package(){0xD, 4}) + } + }//Device(HDAC) + + Name(DEVA, 0x3) //Replace the CMOS location, Since T-SEG SMM can not call INT10 any more + + Device(VGA) // Device + { + Name(_ADR,0x10000) + Name(SWIT,0x1) + Method(_DOS,1) // Enable/Disable Output Switching + { + Store(Arg0, SWIT) // Store the argument as the switch + } + + Method(_INI,0) // Enable Initial display + { + // BIOS don't switch display, but change _DGS + // Video Extension is used to help in switching . + store(DEVA, Local1) + + + If( LNotEqual(And(Local1, 0x2), 0x00) ) // LCD Turn On + { + Store( 0x1, \_SB.PCI0.VGA.LCD._DGS) + } + Else + { + Store( 0x0, \_SB.PCI0.VGA.LCD._DGS) + } + } + + + Name(_DOD,Package() //Package + { + 0x00010110, //LCD, detectable by BIOS + }) + + Device(LCD) + { + Name(_ADR,0x0110) + Name(_DCS,0x1F) //Return the status of output device + Name(_DGS,1) //Query Graphics Desired State + Method(_DSS,1) // Device Set State + { + // Device Set State + If(And(Arg0,0xC0000000)) + { + //If Bit30=1, don't do actual switching, but change _DGS to next state. + If(LEqual(And(Arg0,0x40000000), 0x00)) + { + Store(Arg0, Local0) + Store(And(Local0,0x1),Local0) + Store(Not(0x1), Local1) + Store(And(\_SB.PCI0.VGA.LCD._DGS, Local1), \_SB.PCI0.VGA.LCD._DGS) + Store(Or(\_SB.PCI0.VGA.LCD._DGS, Local0),\_SB.PCI0.VGA.LCD._DGS) + } + } + } + Method(_BCL) { + Return(Package(0x8) { + 100, + 50, + 20, + 30, + 40, + 60, + 80, + 90, + }) + } + Method(_BCM, 1) { + // Store(Arg0, \_SB.PCI0.PIB.PORT80) + } + } + } + + } // Device(PCI0) + + //----------------------------------------------------------------------- + // System board extension Device node for ACPI BIOS + //----------------------------------------------------------------------- + /* + + Procedure: RMEM + + Description: System board extension Device node for ACPI BIOS + Place the device under \_SB scope, As per Msft the MEM + Device is used to reserve Resources that are decoded out of PCI Bus + Important consideration : + Logic to reserve the memory within 0xC0000 - 0xFFFFF Extended BIOS area is based on assumption, + that the BIOS Post has detected all expansion ROMs in the region and made their memory ranges + shadowable ( copied to RAM at the same address, for performance reasons). + The rest of the region is left non-Shadowable, hence no memory is decoded there. + Such region is decoded to PCI bus (to be reserved in PCI0._CRS) + Whatever memory is Shadowed, thus, decoded as non "FF"s, is required to be reserved in "SYSM" + System board extension Device node, unless is not already reserved by some of PCI Device drivers. + There have been observed the difference of how Win9x & Win2000 + OSes deal with Expansion ROM memory. Win9x Device drivers are tend to claim its expension ROMs regions as used + by the device; Win2000 never use such ROM regions for its devices. Therefore there can be different + approach used for different OSes in reservation unclaimed memory in "SYSM" Device node. + is forwarded to PCI Bus + + Input: Nothing + + Output: _CRS buffer + + **************************************************************************/ + + Device(RMEM) { + Name(_HID, EISAID("PNP0C01")) // Hardware Device ID, System Board + Name(_UID, 1) + Name(CRS, ResourceTemplate() + { + // Base Address 0 - 0x9FFFF , 640k DOS memory + Memory32Fixed(ReadWrite,0x0000, 0xA0000 ) //Writeable + // Shadow RAM1, C0000 - E0000, 128k Expansion BIOS + Memory32Fixed(ReadOnly, 0x00000, 0x00000, RAM1) //Non-writeable + // Shadow RAM2, E0000 - 1M, 128k System BIOS + Memory32Fixed(ReadOnly, 0xE0000, 0x20000, RAM2) //Non-writeable + // Base Address 1M - Top of system present memory + Memory32Fixed(ReadWrite,0x100000,0x00000, RAM3) //Writeable + }) + + Method (_CRS, 0) + { + CreateDWordField(CRS, ^RAM1._BAS, BAS1) + CreateDWordField(CRS, ^RAM1._LEN, LEN1) + CreateDWordField(CRS, ^RAM2._BAS, BAS2) + CreateDWordField(CRS, ^RAM2._LEN, LEN2) + CreateDWordField(CRS, ^RAM3._LEN, LEN3) + + //RAM3 + Store(\_SB.PCI0.MEMC.LTMA, Local0) + ShiftLeft(Local0, 0x10, Local2) + Store(\_SB.PCI0.MEMC.ENIG, Local1) + If(LEqual(Local1, 1)) // Check whether the Internal Graphic is enabled. + { + Add(\_SB.PCI0.MEMC.FBSZ, 2, Local3) + ShiftLeft(1, Local3, Local4) + ShiftLeft(Local4, 0x14, Local4) + Subtract(Local2, Local4, Local2) // Subtract the Framebuffer Size + } + Store(\_SB.PCI0.MEMC.ENTS, Local1) + If(LEqual(Local1, 1)) // Check Whether the Top SMRAM Segment is Enabled + { + ShiftLeft(1, \_SB.PCI0.MEMC.TSMS, Local5) + ShiftLeft(Local5, 0x14, Local5) + Subtract(Local2, Local5, Local2) // Subtract Top SM RAM Size + } + Subtract(Local2, 0x100000, LEN3) + + Return(CRS) + } + } + +}//Scope(\_SB) +} Modified: cpu/x86/pc/olpc/via/dsdt.bth ============================================================================== --- cpu/x86/pc/olpc/via/dsdt.bth Wed May 18 05:37:42 2011 (r2201) +++ cpu/x86/pc/olpc/via/dsdt.bth Thu May 19 08:11:17 2011 (r2202) @@ -4,6 +4,7 @@ build-now " iasl -p dsdt -vi -vr -vs ../dsdt.dsl" expand$ $sh +" iasl -p dsdt-c2only -vi -vr -vs ../dsdt-c2only.dsl" expand$ $sh \ " iasl -vi -vr -vs ../fadt.dsl" expand$ $sh \ " iasl -vi -vr -vs ../ssdt.dsl" expand$ $sh Modified: cpu/x86/pc/olpc/via/fw-version.fth ============================================================================== --- cpu/x86/pc/olpc/via/fw-version.fth Wed May 18 05:37:42 2011 (r2201) +++ cpu/x86/pc/olpc/via/fw-version.fth Thu May 19 08:11:17 2011 (r2202) @@ -1,3 +1,3 @@ \ The overall firmware revision macro: FW_MAJOR B -macro: FW_MINOR 03 +macro: FW_MINOR 04 Modified: cpu/x86/pc/olpc/via/olpc.bth ============================================================================== --- cpu/x86/pc/olpc/via/olpc.bth Wed May 18 05:37:42 2011 (r2201) +++ cpu/x86/pc/olpc/via/olpc.bth Thu May 19 08:11:17 2011 (r2202) @@ -160,8 +160,9 @@ " ${BP}/cpu/x86/pc/olpc/images/Edge1-8k-EQ-Comp-Amp-Short.wav" " splash" $add-deflated-dropin - " ${BP}/cpu/x86/pc/olpc/via/build/dsdt.aml" " dsdt" $add-deflated-dropin -\ " ${BP}/cpu/x86/pc/olpc/via/build/ssdt.aml" " ssdt" $add-deflated-dropin + " ${BP}/cpu/x86/pc/olpc/via/build/dsdt.aml" " dsdt" $add-deflated-dropin + " ${BP}/cpu/x86/pc/olpc/via/build/dsdt-c2only.aml" " dsdt-c2only" $add-deflated-dropin +\ " ${BP}/cpu/x86/pc/olpc/via/build/ssdt.aml" " ssdt" $add-deflated-dropin \ icons for mfg test gui " testicons/play.565" " play.565" $add-deflated-dropin

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[commit] r2201 - cpu/arm/olpc/1.75
by repository service 18 May '11

18 May '11

Author: quozl Date: Wed May 18 05:37:42 2011 New Revision: 2201 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2201 Log: OLPC XO-1.75 - reuire battery and external power on flash-ec, #10698, untested. Modified: cpu/arm/olpc/1.75/ecflash.fth Modified: cpu/arm/olpc/1.75/ecflash.fth ============================================================================== --- cpu/arm/olpc/1.75/ecflash.fth Wed May 18 03:48:02 2011 (r2200) +++ cpu/arm/olpc/1.75/ecflash.fth Wed May 18 05:37:42 2011 (r2201) @@ -34,8 +34,7 @@ ifd @ fclose ( len ) load-base swap ?ec-image-valid ; -: flash-ec ( "filename" -- ) - get-ec-file +: reflash-ec [ifdef] cl2-a1 " enter-updater" $call-ec ." Erasing ..." cr " erase-flash" $call-ec cr @@ -47,7 +46,7 @@ ." Erasing ..." erase-chip cr ." Writing ..." load-base /ec-flash 0 edi-program-flash cr ." Verifying ..." - load-base /ec-flash + /ec-flash 0 edi-read-flash + load-base /ec-flash + /ec-flash 0 edi-read-flash [then] load-base load-base /ec-flash + /ec-flash comp abort" Miscompare!" @@ -59,6 +58,8 @@ [then] reset-ec ; +: flash-ec ( "filename" -- ) get-ec-file ?enough-power reflash-ec ; +: flash-ec! ( "filename" -- ) get-ec-file reflash-ec ; : read-ec-flash ( -- ) [ifdef] cl2-a1 " enter-updater" $call-ec

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[commit] r2200 - ofw/termemu
by repository service 18 May '11

18 May '11

Author: wmb Date: Wed May 18 03:48:02 2011 New Revision: 2200 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2200 Log: Added 565>rgb function. Modified: ofw/termemu/fb8.fth Modified: ofw/termemu/fb8.fth ============================================================================== --- ofw/termemu/fb8.fth Sat May 14 02:49:07 2011 (r2199) +++ ofw/termemu/fb8.fth Wed May 18 03:48:02 2011 (r2200) @@ -78,6 +78,11 @@ swap 2 rshift 5 lshift or swap 3 rshift d# 11 lshift or ; +: 565>rgb ( w -- r g b ) + dup d# 8 rshift 7 or + over 3 rshift h# fc and 3 or + rot 3 lshift h# f8 and 7 or +; create colors-8bpp 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , a , b , c , d , e , f ,

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[commit] r2199 - cpu/arm/marvell
by repository service 14 May '11

14 May '11

Author: wmb Date: Sat May 14 02:49:07 2011 New Revision: 2199 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2199 Log: OLPC XO-1.75 - Changed some values for the USB OTG PHY to match values I got from some source code drop. Modified: cpu/arm/marvell/utmiphy.fth Modified: cpu/arm/marvell/utmiphy.fth ============================================================================== --- cpu/arm/marvell/utmiphy.fth Fri May 13 00:09:17 2011 (r2198) +++ cpu/arm/marvell/utmiphy.fth Sat May 14 02:49:07 2011 (r2199) @@ -6,6 +6,7 @@ h# d420700c constant utmi-tx h# d4207010 constant utmi-rx h# d4207014 constant utmi-ivref +h# d4207018 constant utmi-t0 : regset ( mask adr -- ) tuck l@ or swap l! ; : regclr ( mask adr -- ) tuck l@ swap invert and swap l! ; @@ -16,14 +17,16 @@ loop ." PLL calibrate timeout" cr ; -h# 7e03.ffff value pll-clr \ PLLCALI12, PLLVDD18, PLLVDD12, KVCO, ICP, FBDIV, REFDIV, -h# 7e01.aeeb value pll-set \ 3 3 3 3 2 ee b +\ h# 7e03.ffff value pll-clr \ PLLCALI12, PLLVDD18, PLLVDD12, KVCO, ICP, FBDIV, REFDIV, +\ h# 7e01.aeeb value pll-set \ 3 3 3 3 2 ee b +h# 0003.ffff value pll-clr \ KVCO, ICP, FBDIV, REFDIV, +h# 7e01.9eeb value pll-set \ 3 3 3 3 1 ee b h# 00df.c000 value tx-clr \ TXVDD12, CK60_PHSEL, IMPCAL_VTH -h# 00c9.4000 value tx-set \ 3 4 5 +h# 00c8.0000 value tx-set \ 3 4 0 -h# 0001.80f0 value rx-clr \ REG_SQ_LENGTH, RX_SQ_THRESH -h# 0001.000a value rx-set \ 2 a +h# 0000.00f0 value rx-clr \ RX_SQ_THRESH +h# 0000.0070 value rx-set \ 7 : init-usb-phy ( -- ) [ifdef] notdef @@ -35,19 +38,27 @@ \ Turn on the USB PHY power h# 1010.0000 utmi-ctrl regset \ INPKT_DELAY_SOF, PU_REF h# 2 utmi-ctrl regset \ PLL_PWR_UP + d# 10 ms h# 1 utmi-ctrl regset \ PWR_UP + 1 ms + + \ Linux code does this, perhaps redundantly + h# 1000.0000 utmi-ctrl regset \ INPKT_DELAY_SOF, PU_REF + + h# 0000.8000 utmi-t0 regclr \ REG_FIFO_SQ_RST \ Configure the PLLs pll-clr utmi-pll regclr \ PLLCALI12, PLLVDD18, PLLVDD12, KVCO, ICP, FBDIV, REFDIV, - pll-set utmi-pll regset \ 3 3 3 3 2 ee b + pll-set utmi-pll regset \ 3 3 3 3 1 ee b + 1 ms tx-clr utmi-tx regclr \ TXVDD12, CK60_PHSEL, IMPCAL_VTH - tx-set utmi-tx regset \ 3 4 5 + tx-set utmi-tx regset \ 3 4 0 - rx-clr utmi-rx regclr \ REG_SQ_LENGTH, RX_SQ_THRESH - rx-set utmi-rx regset \ 2 a + rx-clr utmi-rx regclr \ RX_SQ_THRESH + rx-set utmi-rx regset \ 7 - d# 10000 wait-cal + d# 1000 wait-cal d# 200 us h# 0020.0000 utmi-pll regset \ VCOCAL_START

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[commit] r2198 - cpu/x86/pc/olpc
by repository service 13 May '11

13 May '11

Author: wmb Date: Fri May 13 00:09:17 2011 New Revision: 2198 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2198 Log: OLPC RTC anti-rollback - working version. Modified: cpu/x86/pc/olpc/guardrtc.fth cpu/x86/pc/olpc/security.fth Modified: cpu/x86/pc/olpc/guardrtc.fth ============================================================================== --- cpu/x86/pc/olpc/guardrtc.fth Tue May 10 19:56:01 2011 (r2197) +++ cpu/x86/pc/olpc/guardrtc.fth Fri May 13 00:09:17 2011 (r2198) @@ -70,6 +70,7 @@ flash-open ( ) (put-mfg-data) ( ) flash-close ( ) + d# 1000 ms ( ) \ Give the EC time to restart ; : flash-write-some ( adr len offset -- ) flash-open ( adr len offset ) @@ -142,31 +143,41 @@ update-timestamp ( status ) ; -1 buffer: byte-buf -: encode-byte ( b -- ) byte-buf c! byte-buf 1 encode-bytes ; : +encode-bytes ( prop$ $ -- prop$' ) encode-bytes encode+ ; -: make-timestamp-property ( -- ) - rtc-timestamp 0= if exit then - " /chosen" find-package drop push-package ( ) - rtc-timestamp unix-seconds> ( s m h d m y ) - push-decimal ( s m h d m y ) - #timestamps (.) encode-bytes ( s m h d m y prop$ ) - " ," +encode-bytes rot (.4) +encode-bytes ( s m h d m prop$ ) - " -" +encode-bytes rot (.2) +encode-bytes ( s m h d prop$' ) - " -" +encode-bytes rot (.2) +encode-bytes ( s m h prop$' ) - " @" +encode-bytes rot (.2) +encode-bytes ( s m prop$' ) - " :" +encode-bytes rot (.2) +encode-bytes ( s prop$' ) - " :" +encode-bytes rot (.2) +encode-bytes ( prop$' ) - " "(00)" +encode-bytes ( prop$' ) - pop-base ( ) - - " rtc-timestamp" (property) ( ) - pop-package -; -: make-status-property ( value$ -- ) - " /chosen" find-package drop push-package ( value$ ) +string-array rtc-status-names + ," ok" + ," empty" + ," residue" + ," rollback" +end-string-array + +: make-rtc-properties ( status -- ) + " /chosen" find-package drop push-package ( status ) + + rtc-status-names count encode-string " rtc-status" (property) ( ) + + rtc-timestamp if + rtc-timestamp unix-seconds> ( s m h d m y ) + push-decimal ( s m h d m y ) + (.4) encode-bytes ( s m h d m prop$ ) + rot (.2) +encode-bytes ( s m h d prop$' ) + rot (.2) +encode-bytes ( s m h prop$' ) + " T" +encode-bytes ( s m h prop$' ) + rot (.2) +encode-bytes ( s m prop$' ) + rot (.2) +encode-bytes ( s prop$' ) + rot (.2) +encode-bytes ( prop$' ) + " Z"(00)" +encode-bytes ( prop$' ) + pop-base ( ) + + " rtc-timestamp" (property) ( ) + then + + push-decimal + #timestamps (.) encode-bytes " rtc-count" (property) ( ) + pop-base + pop-package ; @@ -178,24 +189,19 @@ then ( flag ) ; -: rtc-rollback? ( -- flag ) +: rtc-rollback? ( -- error? ) rtcar-enabled? 0= if exit then find-timestamp ( status ) ?update-timestamp ( status' ) - make-timestamp-property ( status ) - case - 0 of " ok" make-status-property false endof - 1 of " empty" make-status-property false endof - 2 of " residue" make-status-property true endof - 3 of " rollback" make-status-property true endof - ( default ) true swap - endcase + dup make-rtc-properties ( status ) + 2 >= ( error? ) ; -: parse-field ( val$ delimiter expected-length -- val$' field$ ) - >r left-parse-string ( val$' field$ ) - dup r> <> throw +: parse-field ( val$ length -- val$' field$ ) + 2dup < throw ( val$ length ) + >r over r@ ( val$ adr length r: length ) + 2swap r> /string 2swap ( val$' field$ ) ; \ Throws an error if either a number is unparsable or out of range : decode-number ( field$ min max -- n ) @@ -206,48 +212,47 @@ ; : decode-timestamp ( val$ -- s m h d m y ) - [char] - 4 parse-field d# 2000 d# 2099 decode-number >r ( val$' r: y ) - [char] - 2 parse-field 1 d# 12 decode-number >r ( val$' r: y m ) - [char] @ 2 parse-field 1 d# 31 decode-number >r ( val$' r: y m d ) - [char] : 2 parse-field 0 d# 23 decode-number >r ( val$' r: y m d h ) - [char] : 2 parse-field 0 d# 59 decode-number >r ( val$' r: y m d h m ) - dup 2 <> throw 0 d# 59 decode-number >r ( r: y m d h m s ) - r> r> r> r> r> r> ( s m h d m y ) -; -: fix-rtc-timestamps ( data$ -- ) \ "count old-ts new-ts" e.g. 2011-10-12,00:23:45 - bl left-parse-string ( rem$ count$ ) - - 0 h# 7fffffff ['] decode-number catch if ( rem$ x x x x ) - 4drop 2drop ." Bad count format" cr ( ) - exit ( -- ) - then ( rem$ count ) - -rot ( count rem$ ) - - find-timestamp ( count rem$ ) - - bl left-parse-string ( count rem$ old-timestamp$ ) - 2dup " no-timestamp" $= if ( count rem$ old-timestamp$ ) - 2drop ( count rem$ ) - rtc-timestamp if ( count rem$ ) - 3drop ( ) + 4 parse-field d# 2000 d# 2099 decode-number >r ( val$' r: y ) + 2 parse-field 1 d# 12 decode-number >r ( val$' r: y m ) + 2 parse-field 1 d# 31 decode-number >r ( val$' r: y m d ) + 1 parse-field drop c@ [char] T <> throw ( val$' r: y m d ) + 2 parse-field 0 d# 23 decode-number >r ( val$' r: y m d h ) + 2 parse-field 0 d# 59 decode-number >r ( val$' r: y m d h m ) + 2 parse-field 0 d# 59 decode-number >r ( val$' r: y m d h m s ) + 1 parse-field drop c@ [char] Z <> throw ( val$' r: y m d h m s ) + nip 0<> throw ( r: y m d h m s ) + r> r> r> r> r> r> ( s m h d m y ) +; +: fix-rtc-timestamps ( newrtc$ nonce$ -- currentrtc$ ) + find-timestamp drop ( newrtc$ nonce$ currentrtc$ ) + + 2dup " 00000000T000000Z" $= if ( newrtc$ nonce$ currentrtc$ ) + 2drop ( newrtc$ nonce$ ) + rtc-timestamp if ( newrtc$ nonce$ ) + 4drop ( ) ." Old timestamp mismatch" cr ( ) exit ( -- ) - then - else ( count rem$ old-timestamp$ ) - ['] decode-timestamp catch if ( count rem$ x x ) - 5drop ( ) + then ( newrtc$ nonce$ ) + else ( newrtc$ nonce$ currentrtc$ ) + ['] decode-timestamp catch if ( newrtc$ nonce$ x x ) + 2drop 4drop ( ) ." Bad timestamp format" cr ( ) exit ( -- ) - then ( count rem$ s m h d m y ) - then ( count rem$ s m h d m y ) + then ( newrtc$ nonce$ s m h d m y ) + >unix-seconds ( newrtc$ nonce$ timestamp ) + rtc-timestamp <> if ( newrtc$ nonce$ ) + 4drop ( ) + ." Old timestamp mismatch" cr ( ) + exit ( -- ) + then ( newrtc$ nonce$ ) + then ( newrtc$ nonce$ ) - >unix-seconds ( count rem$ old-timestamp ) - rtc-timestamp <> if ( count rem$ ) - 3drop ( ) - ." Old timestamp mismatch" cr ( ) + 0 h# 7fffffff ['] decode-number catch if ( newrtc$ x x x x ) + 4drop 2drop ." Bad count format" cr ( ) exit ( -- ) - then ( count rem$ ) - rot init-timestamp-area ( rem$ ) + then ( newrtc$ count ) + + init-timestamp-area ( newrtc$ ) ['] decode-timestamp catch if ( x x ) 2drop ." Bad timestamp format" cr ( ) Modified: cpu/x86/pc/olpc/security.fth ============================================================================== --- cpu/x86/pc/olpc/security.fth Tue May 10 19:56:01 2011 (r2197) +++ cpu/x86/pc/olpc/security.fth Fri May 13 00:09:17 2011 (r2198) @@ -955,37 +955,102 @@ r> to debug-security? ; -: fix-rtc-history ( data$ -- ) \ SN UUID counter timestamp newtimestamp - \ Isolate data from first line + +0 [if] +\ SN : UUID : currrtc : nonce : newrtc +\ 0 11 12 48 49 65 66 76 77 (93) +d# 11 1+ d# 36 + 1+ d# 16 + 1+ d# 10 + 1+ d# 16 + +constant /rtc-signature +/rtc-signature buffer: rtc-signature-buf + +: check-rtc-signature ( sig$ currentrtc$ nonce$ newrtc$ -- good? ) + + rtc-signature-buf d# 77 + swap move ( sig$ currentrtc$ nonce$ ) + [char] : rtc-signature-buf d# 76 + c! ( sig$ currentrtc$ nonce$ ) + + rtc-signature-buf d# 66 + swap move ( sig$ currentrtc$ ) + [char] : rtc-signature-buf d# 65 + c! ( sig$ currentrtc$ ) + + rtc-signature-buf d# 49 + swap move ( sig$ ) + + \ Copy SN:UUID: from machine-id-buf to rtc-signature-buf + machine-id-buf d# 49 rtc-signature-buf move ( sig$ ) + + rtc-signature-buf /rtc-signature 2swap ( data$ sig$ ) + " sha256" signature-good? ( good? ) +; + newrtc$ rtc-signature-buf d# 77 + swap move ( ) + [char] : rtc-signature-buf d# 76 + c! ( ) + + nonce$ rtc-signature-buf d# 66 + swap move ( ) + [char] : rtc-signature-buf d# 65 + c! ( ) + + currentrtc$ rtc-signature-buf d# 49 + swap move ( ) + [char] : rtc-signature-buf d# 48 + c! ( ) + +[then] + +0 0 2value currentrtc$ +0 0 2value newrtc$ +0 0 2value nonce$ +0 0 2value rtcsig$ +: rtc-format-error ( -- done? ) + ." RTC Reset format error" ?lease-error-cr true +; +: check-rtc-key ( data$ -- done? ) \ rtc01: SN currentrtc nonce newrtc sig0N: ... + \ Isolate data from line newline left-parse-string 2nip ( rem$ ) + bl left-parse-string " rtc01:" $= 0= if ( rem$ ) + ." Unknown format" ?lease-error-cr ( rem$ ) + 2drop true exit ( -- true ) + then ( rem$ ) + bl left-parse-string ( rem$ serial$ ) my-sn$ $= 0= if ( rem$ ) - ." Wrong serial number" ?lease-error-cr ( rem$ ) - 2drop exit ( -- ) +\ ." Wrong serial number" ?lease-error-cr ( rem$ ) + 2drop false exit ( -- false ) then ( rem$ ) - \ Ignore UUID for now - bl left-parse-string ( rem$ uuid$ ) - 2drop ( rem$ ) - - fix-rtc-timestamps ( ) + bl left-parse-string to currentrtc$ ( rem$' ) + bl left-parse-string to nonce$ ( rem$' ) + bl left-parse-string to newrtc$ ( rem$' ) + to rtcsig$ ( ) + + currentrtc$ nip d# 16 <> if rtc-format-error exit then + nonce$ nip d# 10 <> if rtc-format-error exit then + newrtc$ nip d# 16 <> if rtc-format-error exit then + + newrtc$ nonce$ currentrtc$ machine-id-buf d# 48 " %s:%s:%s:%s" sprintf ( data$ ) + + rtcsig$ " sha256" signature-good? if ( ) + newrtc$ nonce$ currentrtc$ fix-rtc-timestamps ( ) + else + ." Bad signature " ?lease-error-cr ( ) + then ( ) + true ( done? ) ; : ?rtc-update ( -- ) rtcar-enabled? 0= if exit then show-dot null$ cn-buf place - " rtcreset" bundle-present? if + " rtcreset.sig" open-security? if exit then >r ( r: ih ) " RTCRESET found - " ?lease-debug + load-started leasekey$ to pubkey$ - img$ sig$ sha-valid? if - img$ fix-rtc-history - show-unlock - else - show-lock - then - then + begin + sec-line-buf /sec-line-max r@ read-line if ( actual -eof? ) + 2drop r> close-file drop exit + then ( actual -eof? ) + while ( actual ) + sec-line-buf swap check-rtc-key if ( ) + r> close-file drop exit ( -- ) + then ( ) + repeat ( actual ) + drop ( ) + " No matching records" ?lease-error-cr ( ) + r> close-file drop false ( false ) ; : load-from-device ( devname$ -- done? )

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[commit] r2197 - in cpu/arm: mmp2 olpc/1.75
by repository service 10 May '11

10 May '11

Author: wmb Date: Tue May 10 19:56:01 2011 New Revision: 2197 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2197 Log: OLPC XO-1.75 - new improved clock speed setting tools. Added: cpu/arm/mmp2/clocks.fth Modified: cpu/arm/olpc/1.75/fw.bth Added: cpu/arm/mmp2/clocks.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/clocks.fth Tue May 10 19:56:01 2011 (r2197) @@ -0,0 +1,35 @@ +purpose: Change the clock frequency + +: fccr@ ( -- n ) h# d405.0008 l@ ; +: fccr! ( n -- ) h# d405.0008 l! ; +: pj4-clksel ( n -- ) + d# 29 lshift ( field ) + fccr@ h# e000.0000 invert and or fccr! ( ) +; +: sp-clksel ( n -- ) + d# 26 lshift ( field ) + fccr@ h# 1c00.0000 invert and or fccr! ( ) +; +: pj4-cc! ( n -- ) h# d428.2804 l! ; + +: sp-cc! ( n -- ) h# d428.2800 l! ; +\ cfraaADXBpP +: sp-100mhz ( -- ) 0 sp-clksel o# 37077703303 sp-cc! ; \ A 100, D 400, XP 100, B 100, P 100 +: sp-200mhz ( -- ) 0 sp-clksel o# 37077301101 sp-cc! ; \ A 200, D 400, XP 200, B 200, P 200 +: sp-400mhz1 ( -- ) 0 sp-clksel o# 37077301100 sp-cc! ; \ A 200, D 400, XP 200, B 200, P 400 +: sp-400mhz2 ( -- ) 0 sp-clksel o# 37077300000 sp-cc! ; \ A 200, D 400, XP 400, B 400, P 400 +: sp-original 1 sp-clksel o# 37077301101 sp-cc! ; \ A 200, D 400, XP 400, B 400, P 400 + +\ cfr52ADXBCP +: pj4-100mhz ( -- ) 0 pj4-clksel o# 37042703303 pj4-cc! ; \ A 100, D 400, XP 100, B 100, P 100 +: pj4-200mhz ( -- ) 0 pj4-clksel o# 37042301101 pj4-cc! ; \ A 200, D 400, XP 200, B 200, P 200 +: pj4-400mhz ( -- ) 0 pj4-clksel o# 37042301100 pj4-cc! ; \ A 200, D 400, XP 200, B 200, P 400 +: pj4-800mhz ( -- ) 1 pj4-clksel o# 37042201100 pj4-cc! ; \ A 266, D 400, XP 400, B 400, P 800 + +0 [if] +\ PJ4 versions using voting cvr52ADXBCP +: pj4-100mhz ( -- ) 0 pj4-clksel o# 21742703303 pj4-cc! ; \ A 100, D 400, XP 100, B 100, P 100 +: pj4-200mhz ( -- ) 0 pj4-clksel o# 21742301101 pj4-cc! ; \ A 200, D 400, XP 200, B 200, P 200 +: pj4-400mhz ( -- ) 0 pj4-clksel o# 21742301100 pj4-cc! ; \ A 200, D 400, XP 200, B 200, P 400 +: pj4-800mhz ( -- ) 1 pj4-clksel o# 21742201100 pj4-cc! ; \ A 266, D 400, XP 400, B 400, P 800 +[then] Modified: cpu/arm/olpc/1.75/fw.bth ============================================================================== --- cpu/arm/olpc/1.75/fw.bth Tue May 10 19:53:29 2011 (r2196) +++ cpu/arm/olpc/1.75/fw.bth Tue May 10 19:56:01 2011 (r2197) @@ -362,16 +362,7 @@ game-key-mask = if protect-fw try-fs-update then ; -\ fload ${BP}/cpu/arm/mmp2/clocks.fth - -\ 0 [if] -: 400mhz ( -- ) - h# d428.2804 l@ 7 invert and h# 7000.0000 or 1 or h# d428.2804 l! -; -: 800mhz ( -- ) - h# d428.2804 l@ 7 invert and h# 7000.0000 or h# d428.2804 l! -; -\ [then] +fload ${BP}/cpu/arm/mmp2/clocks.fth : startup ( -- ) standalone? 0= if exit then

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[commit] r2196 - cpu/arm/mmp2 cpu/arm/olpc/1.75 cpu/x86/pc/olpc cpu/x86/pc/olpc/via dev/olpc/kb3700 dev/olpc/spiflash
by repository service 10 May '11

10 May '11

Author: wmb Date: Tue May 10 19:53:29 2011 New Revision: 2196 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2196 Log: OLPC - RTC Anti-rollback security feature - initial checkin. Added: cpu/x86/pc/olpc/guardrtc.fth Modified: cpu/arm/mmp2/sspspi.fth cpu/arm/olpc/1.75/devices.fth cpu/arm/olpc/1.75/fw.bth cpu/x86/pc/olpc/fw.bth cpu/x86/pc/olpc/security.fth cpu/x86/pc/olpc/setwp.fth cpu/x86/pc/olpc/via/fw.bth dev/olpc/kb3700/ecio.fth dev/olpc/spiflash/flashif.fth dev/olpc/spiflash/spiflash.fth Modified: cpu/arm/mmp2/sspspi.fth ============================================================================== --- cpu/arm/mmp2/sspspi.fth Tue May 10 01:27:14 2011 (r2195) +++ cpu/arm/mmp2/sspspi.fth Tue May 10 19:53:29 2011 (r2196) @@ -24,12 +24,105 @@ : ssp-spi-cs-on ( -- ) d# 46 gpio-clr ; : ssp-spi-cs-off ( -- ) d# 46 gpio-set ; +code ssp-spi-out-in ( bo -- bi ) + set r0,`ssp-base #` + begin + ldr r1,[r0,#8] + ands r1,r1,#4 + 0<> until + str tos,[r0,#0x10] + begin + ldr r1,[r0,#8] + ands r1,r1,#8 + 0<> until + ldr tos,[r0,#0x10] +c; +0 [if] : ssp-spi-out-in ( bo -- bi ) begin ssp-sssr l@ 4 and until \ Tx not full ssp-ssdr l! begin ssp-sssr l@ 8 and until \ Rx not empty ssp-ssdr l@ ; +[then] +code ssp-spi-in16 ( adr -- adr' ) + set r0,`ssp-base #` + set r2,#0xf04 + set r3,#0xf008 + mov r4,#0 + begin + ldr r1,[r0,#8] + and r1,r1,r2 + cmp r1,#4 + 0= until + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + str r4,[r0,#0x10] + begin + ldr r1,[r0,#8] + and r1,r1,r3 + cmp r1,r3 + 0= until + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 + ldr r4,[r0,#0x10] + strb r4,[tos],#1 +c; +: fast-spi-flash-read ( adr len offset -- ) + 3 spi-cmd spi-adr ( adr len ) + d# 16 /mod ( adr len%16 len/16 ) + swap >r ( adr len/16 r: len%16 ) + 0 ?do ( adr r: len%16 ) + ssp-spi-in16 ( adr' r: len%16 ) + loop ( adr' r: len%16 ) + r> 0 ?do ( adr ) + spi-in over c! ( adr ) + 1+ ( adr' ) + loop ( adr ) + drop ( ) + spi-cs-off ( ) +; : ssp-spi-out ( b -- ) ssp-spi-out-in drop ; : ssp-spi-in ( -- b ) 0 ssp-spi-out-in ; @@ -48,8 +141,10 @@ ['] ssp-spi-out to spi-out ['] ssp-spi-cs-on to spi-cs-on ['] ssp-spi-cs-off to spi-cs-off - ['] ssp-spi-reprogrammed to spi-reprogrammed - use-spi-flash-read + ['] noop to spi-reprogrammed + ['] noop to spi-reprogrammed-no-reboot +\ use-spi-flash-read + ['] fast-spi-flash-read to flash-read ; use-ssp-spi Modified: cpu/arm/olpc/1.75/devices.fth ============================================================================== --- cpu/arm/olpc/1.75/devices.fth Tue May 10 01:27:14 2011 (r2195) +++ cpu/arm/olpc/1.75/devices.fth Tue May 10 19:53:29 2011 (r2196) @@ -103,7 +103,6 @@ fload ${BP}/dev/olpc/spiflash/spiflash.fth \ SPI FLASH programming : ignore-power-button ; \ XXX implement me -: ssp-spi-reprogrammed ; fload ${BP}/cpu/arm/mmp2/sspspi.fth \ Synchronous Serial Port SPI interface Modified: cpu/arm/olpc/1.75/fw.bth ============================================================================== --- cpu/arm/olpc/1.75/fw.bth Tue May 10 01:27:14 2011 (r2195) +++ cpu/arm/olpc/1.75/fw.bth Tue May 10 19:53:29 2011 (r2196) @@ -229,6 +229,7 @@ ; code halt ( -- ) wfi c; fload ${BP}/cpu/x86/pc/olpc/sound.fth +fload ${BP}/cpu/x86/pc/olpc/guardrtc.fth fload ${BP}/cpu/x86/pc/olpc/security.fth : pre-setup-for-linux ( -- ) @@ -361,12 +362,16 @@ game-key-mask = if protect-fw try-fs-update then ; +\ fload ${BP}/cpu/arm/mmp2/clocks.fth + +\ 0 [if] : 400mhz ( -- ) h# d428.2804 l@ 7 invert and h# 7000.0000 or 1 or h# d428.2804 l! ; : 800mhz ( -- ) h# d428.2804 l@ 7 invert and h# 7000.0000 or h# d428.2804 l! ; +\ [then] : startup ( -- ) standalone? 0= if exit then Modified: cpu/x86/pc/olpc/fw.bth ============================================================================== --- cpu/x86/pc/olpc/fw.bth Tue May 10 01:27:14 2011 (r2195) +++ cpu/x86/pc/olpc/fw.bth Tue May 10 19:53:29 2011 (r2196) @@ -361,6 +361,7 @@ fload ${BP}/cpu/x86/pc/olpc/setwp.fth fload ${BP}/cpu/x86/pc/olpc/sound.fth +fload ${BP}/cpu/x86/pc/olpc/guardrtc.fth fload ${BP}/cpu/x86/pc/olpc/security.fth fload ${BP}/cpu/x86/pc/olpc/xpsecure.fth fload ${BP}/ofw/gui/ofpong.fth Added: cpu/x86/pc/olpc/guardrtc.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/x86/pc/olpc/guardrtc.fth Tue May 10 19:53:29 2011 (r2196) @@ -0,0 +1,282 @@ +\ See license at end of file +purpose: Real-Time Clock Anti-rollback for security + +\ The entry points are: +\ rtcar-enabled? ( -- flag ) +\ True if an "rt" tag is present in manufacturing data, thus enabling anti-rollback +\ rtc-rollback? ( -- flag ) +\ True if either a rollback attach is detected or the timestamp area is corrupt +\ fix-rtc-timestamps ( data$ -- ) \ "count old-timestamp new-timestamp" +\ Restores valid data in the timestamp area according to data$ + +\ Layout of timestamp area: +\ Bytes 0-3 - 4-byte rewrite count - little-endian +\ Bytes 4-8 - Timestamp 0 +\ Bytes 9-13 - Timestamp 1 +\ ... +\ Bytes 32759-32763 - Timestamp 6552 +\ Each timestamp is a 4-byte little-endian "unixtime" (seconds since +\ epoch), followed by a 1-byte xor checksum of the preceding 4 bytes ^ 0x55 + +5 constant /timestamp + +\ First 4 bytes are the write counter base value +/l constant timestamp-start +d# 32768 timestamp-start - /timestamp / constant #timestamps/rewrite +#timestamps/rewrite /timestamp * constant /timestamps + +0 value timestamp-offset +0 value rtc-timestamp +0 value new-timestamp +: +tsbuf ( offset -- adr ) mfg-data-buf + ; +: timestamp-adr ( -- adr ) timestamp-offset +tsbuf timestamp-start + ; +: compute-check-byte ( timestamp -- check ) + lbsplit xor xor xor h# 55 xor +; +: count-base@ ( -- n ) 0 +tsbuf le-l@ ; +: count-base! ( n -- ) 0 +tsbuf le-l! ; +: #timestamps ( timestamp-offset -- n ) + timestamp-offset /timestamp / ( #buffered-timestamps ) + count-base@ + ( n ) +; +: timestamp-bad? ( -- timestamp error? ) + timestamp-adr le-l@ ( timestamp ) + dup compute-check-byte ( timestamp computed-check ) + timestamp-adr la1+ c@ <> ( timestamp error ) +; +: set-timestamp-offset ( -- error? ) + 0 to timestamp-offset ( ) + 0 to rtc-timestamp + begin timestamp-offset /timestamps <> while ( ) + timestamp-adr le-l@ h# ffffffff = if ( ) + \ Verify that the rest of the area is all ff too + timestamp-adr /timestamps timestamp-offset - ( adr len ) + h# ff bskip 0<> ( error? ) + exit ( -- error? ) + then ( ) + timestamp-bad? if ( timestamp ) + drop ( ) + true exit \ Bad checksum ( -- error? ) + else ( timestamp ) + to rtc-timestamp ( ) + then ( ) + + timestamp-offset /timestamp + to timestamp-offset ( ) + repeat ( ) + false ( ) +; + +: commit-timestamp-area ( -- ) + flash-open ( ) + (put-mfg-data) ( ) + flash-close ( ) +; +: flash-write-some ( adr len offset -- ) + flash-open ( adr len offset ) + flash-write ( ) + flash-close ( ) +; +: init-timestamp-area ( base -- ) + count-base! ( ) + + timestamp-start +tsbuf /timestamps h# ff bskip if ( ) + \ There is junk in the timestamp area so we must erase and rewrite + timestamp-start +tsbuf /timestamps h# ff fill ( ) + commit-timestamp-area + else + \ The timestamp area is already erased, so we can write without erasing + mfg-data-buf /l mfg-data-offset flash-write-some + then + + 0 to timestamp-offset +; +: rewrite-timestamp-area ( -- ) + \ Fill the timestamp area with ff's + timestamp-start +tsbuf /timestamps /timestamp /string h# ff fill + + \ Update the rewrite count + count-base@ #timestamps/rewrite + count-base! + + \ Perform an erase and rewrite on the mfg data area + commit-timestamp-area +; +: update-timestamp ( -- ) + timestamp-offset /timestamps = if ( ) + rewrite-timestamp-area ( ) + 0 to timestamp-offset ( ) + then + + new-timestamp dup timestamp-adr le-l! ( unixtime ) + compute-check-byte timestamp-adr la1+ c! ( ) + timestamp-adr /timestamp timestamp-offset timestamp-start + mfg-data-offset + flash-write-some ( ) +; + +: find-timestamp ( -- status ) + get-mfg-data ( ) + + count-base@ h# ffffffff = if ( ) + 0 init-timestamp-area ( ) + then ( ) + + set-timestamp-offset if ( ) + \ There is bad data after the last timestamp, if any + 2 exit ( -- 1 ) + then ( ) + + timestamp-offset 0= if ( ) + \ There is no data in the timestamp area + 1 exit ( -- 2 ) + then ( ) + 0 ( -- 0 ) +; +: ?update-timestamp ( status -- status' ) + dup 1 > if exit then ( status ) + + time&date >unix-seconds to new-timestamp ( status ) + + new-timestamp rtc-timestamp <= if ( status ) + \ Time went backwards + drop 3 exit ( -- status' ) + then ( status ) + + update-timestamp ( status ) +; + +1 buffer: byte-buf +: encode-byte ( b -- ) byte-buf c! byte-buf 1 encode-bytes ; +: +encode-bytes ( prop$ $ -- prop$' ) encode-bytes encode+ ; + +: make-timestamp-property ( -- ) + rtc-timestamp 0= if exit then + " /chosen" find-package drop push-package ( ) + rtc-timestamp unix-seconds> ( s m h d m y ) + push-decimal ( s m h d m y ) + #timestamps (.) encode-bytes ( s m h d m y prop$ ) + " ," +encode-bytes rot (.4) +encode-bytes ( s m h d m prop$ ) + " -" +encode-bytes rot (.2) +encode-bytes ( s m h d prop$' ) + " -" +encode-bytes rot (.2) +encode-bytes ( s m h prop$' ) + " @" +encode-bytes rot (.2) +encode-bytes ( s m prop$' ) + " :" +encode-bytes rot (.2) +encode-bytes ( s prop$' ) + " :" +encode-bytes rot (.2) +encode-bytes ( prop$' ) + " "(00)" +encode-bytes ( prop$' ) + pop-base ( ) + + " rtc-timestamp" (property) ( ) + pop-package +; +: make-status-property ( value$ -- ) + " /chosen" find-package drop push-package ( value$ ) + encode-string " rtc-status" (property) ( ) + pop-package +; + +: rtcar-enabled? ( -- flag ) + " rt" find-tag if ( data$ ) + 2drop true ( flag ) + else ( ) + false ( flag ) + then ( flag ) +; + +: rtc-rollback? ( -- flag ) + rtcar-enabled? 0= if exit then + + find-timestamp ( status ) + ?update-timestamp ( status' ) + make-timestamp-property ( status ) + case + 0 of " ok" make-status-property false endof + 1 of " empty" make-status-property false endof + 2 of " residue" make-status-property true endof + 3 of " rollback" make-status-property true endof + ( default ) true swap + endcase +; + +: parse-field ( val$ delimiter expected-length -- val$' field$ ) + >r left-parse-string ( val$' field$ ) + dup r> <> throw +; +\ Throws an error if either a number is unparsable or out of range +: decode-number ( field$ min max -- n ) + 2>r ( field$ r: min max ) + push-decimal $number pop-base ( n error? r: min max ) + throw ( n r: min max ) + dup 2r> between 0= throw ( n ) +; + +: decode-timestamp ( val$ -- s m h d m y ) + [char] - 4 parse-field d# 2000 d# 2099 decode-number >r ( val$' r: y ) + [char] - 2 parse-field 1 d# 12 decode-number >r ( val$' r: y m ) + [char] @ 2 parse-field 1 d# 31 decode-number >r ( val$' r: y m d ) + [char] : 2 parse-field 0 d# 23 decode-number >r ( val$' r: y m d h ) + [char] : 2 parse-field 0 d# 59 decode-number >r ( val$' r: y m d h m ) + dup 2 <> throw 0 d# 59 decode-number >r ( r: y m d h m s ) + r> r> r> r> r> r> ( s m h d m y ) +; +: fix-rtc-timestamps ( data$ -- ) \ "count old-ts new-ts" e.g. 2011-10-12,00:23:45 + bl left-parse-string ( rem$ count$ ) + + 0 h# 7fffffff ['] decode-number catch if ( rem$ x x x x ) + 4drop 2drop ." Bad count format" cr ( ) + exit ( -- ) + then ( rem$ count ) + -rot ( count rem$ ) + + find-timestamp ( count rem$ ) + + bl left-parse-string ( count rem$ old-timestamp$ ) + 2dup " no-timestamp" $= if ( count rem$ old-timestamp$ ) + 2drop ( count rem$ ) + rtc-timestamp if ( count rem$ ) + 3drop ( ) + ." Old timestamp mismatch" cr ( ) + exit ( -- ) + then + else ( count rem$ old-timestamp$ ) + ['] decode-timestamp catch if ( count rem$ x x ) + 5drop ( ) + ." Bad timestamp format" cr ( ) + exit ( -- ) + then ( count rem$ s m h d m y ) + then ( count rem$ s m h d m y ) + + >unix-seconds ( count rem$ old-timestamp ) + rtc-timestamp <> if ( count rem$ ) + 3drop ( ) + ." Old timestamp mismatch" cr ( ) + exit ( -- ) + then ( count rem$ ) + rot init-timestamp-area ( rem$ ) + + ['] decode-timestamp catch if ( x x ) + 2drop ." Bad timestamp format" cr ( ) + exit ( -- ) + then ( s m h d m y ) + >unix-seconds to new-timestamp ( ) + update-timestamp ( ) +; + +\ LICENSE_BEGIN +\ Copyright (c) 2011 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END Modified: cpu/x86/pc/olpc/security.fth ============================================================================== --- cpu/x86/pc/olpc/security.fth Tue May 10 01:27:14 2011 (r2195) +++ cpu/x86/pc/olpc/security.fth Tue May 10 19:53:29 2011 (r2196) @@ -728,7 +728,11 @@ " ak" find-tag if 2drop " run" else - lease-valid? if " run" else " act" then + rtc-rollback? if + " act" + else + lease-valid? if " run" else " act" then + then then cn-buf place ; @@ -951,6 +955,39 @@ r> to debug-security? ; +: fix-rtc-history ( data$ -- ) \ SN UUID counter timestamp newtimestamp + \ Isolate data from first line + newline left-parse-string 2nip ( rem$ ) + + bl left-parse-string ( rem$ serial$ ) + my-sn$ $= 0= if ( rem$ ) + ." Wrong serial number" ?lease-error-cr ( rem$ ) + 2drop exit ( -- ) + then ( rem$ ) + + \ Ignore UUID for now + bl left-parse-string ( rem$ uuid$ ) + 2drop ( rem$ ) + + fix-rtc-timestamps ( ) +; + +: ?rtc-update ( -- ) + rtcar-enabled? 0= if exit then + show-dot + null$ cn-buf place + " rtcreset" bundle-present? if + " RTCRESET found - " ?lease-debug + leasekey$ to pubkey$ + img$ sig$ sha-valid? if + img$ fix-rtc-history + show-unlock + else + show-lock + then + then +; + : load-from-device ( devname$ -- done? ) show-dot @@ -972,6 +1009,8 @@ then then + ?rtc-update + show-dot ?leased \ Sets cn-buf Modified: cpu/x86/pc/olpc/setwp.fth ============================================================================== --- cpu/x86/pc/olpc/setwp.fth Tue May 10 01:27:14 2011 (r2195) +++ cpu/x86/pc/olpc/setwp.fth Tue May 10 19:53:29 2011 (r2196) @@ -1,3 +1,6 @@ +\ See license at end of file +purpose: Changing manufacturing data - adding and deleting tags + \ Set the write protect tag. This is used to convert unlocked prototype \ machined to locked machines for testing the firmware security. This \ should not be necessary once mass production systems start coming from @@ -217,3 +220,27 @@ $add-tag ( data$ ) free-mem ; + +\ LICENSE_BEGIN +\ Copyright (c) 2007 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END Modified: cpu/x86/pc/olpc/via/fw.bth ============================================================================== --- cpu/x86/pc/olpc/via/fw.bth Tue May 10 01:27:14 2011 (r2195) +++ cpu/x86/pc/olpc/via/fw.bth Tue May 10 19:53:29 2011 (r2196) @@ -406,6 +406,7 @@ fload ${BP}/cpu/x86/firfilter.fth fload ${BP}/cpu/x86/pc/olpc/sound.fth fload ${BP}/cpu/x86/pc/olpc/via/sound.fth +fload ${BP}/cpu/x86/pc/olpc/guardrtc.fth fload ${BP}/cpu/x86/pc/olpc/security.fth fload ${BP}/cpu/x86/pc/olpc/xpsecure.fth fload ${BP}/ofw/gui/ofpong.fth Modified: dev/olpc/kb3700/ecio.fth ============================================================================== --- dev/olpc/kb3700/ecio.fth Tue May 10 01:27:14 2011 (r2195) +++ dev/olpc/kb3700/ecio.fth Tue May 10 19:53:29 2011 (r2196) @@ -348,6 +348,10 @@ ." Restarting..." d# 2000 ms cr kbc-on begin again ; +: io-spi-reprogrammed-no-reboot ( -- ) + no-kbc-reboot + kbc-on +; : io-spi-start ( -- ) ['] io-spi@ to spi@ @@ -356,6 +360,7 @@ use-ec-spi \ spi-in, spi-cs-on, spi-cs-off via EC commands ['] io-spi-reprogrammed to spi-reprogrammed + ['] io-spi-reprogrammed-no-reboot to spi-reprogrammed-no-reboot use-mem-flash-read [ifdef] uncache-flash uncache-flash [then] Modified: dev/olpc/spiflash/flashif.fth ============================================================================== --- dev/olpc/spiflash/flashif.fth Tue May 10 01:27:14 2011 (r2195) +++ dev/olpc/spiflash/flashif.fth Tue May 10 19:53:29 2011 (r2196) @@ -2,6 +2,7 @@ purpose: Generic interface for FLASH programming operations defer flash-open ( -- ) +defer flash-close ( -- ) defer flash-write-enable ( -- ) defer flash-write-disable ( -- ) defer flash-write ( adr len offset -- ) Modified: dev/olpc/spiflash/spiflash.fth ============================================================================== --- dev/olpc/spiflash/spiflash.fth Tue May 10 01:27:14 2011 (r2195) +++ dev/olpc/spiflash/spiflash.fth Tue May 10 19:53:29 2011 (r2196) @@ -219,6 +219,8 @@ defer spi-reprogrammed ( -- ) \ What to do when done reprogramming ' noop to spi-reprogrammed +defer spi-reprogrammed-no-reboot ( -- ) \ What to do when done reprogramming +' noop to spi-reprogrammed-no-reboot defer write-spi-flash ( adr len offset -- ) @@ -312,6 +314,7 @@ \ Install the SPI FLASH versions as their implementations. : use-spi-flash ( -- ) ['] spi-flash-open to flash-open + ['] spi-reprogrammed-no-reboot to flash-close ['] spi-flash-write-enable to flash-write-enable ['] spi-reprogrammed to flash-write-disable ['] write-spi-flash to flash-write

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[commit] r2195 - cpu/x86/pc/olpc/via
by repository service 10 May '11

10 May '11

Author: rsmith Date: Tue May 10 01:27:14 2011 New Revision: 2195 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2195 Log: OLPC XO-1.5: Ver: q3b03 Transition to new EC 2.2.x series code Modified: cpu/x86/pc/olpc/via/ec-version.fth cpu/x86/pc/olpc/via/fw-version.fth Modified: cpu/x86/pc/olpc/via/ec-version.fth ============================================================================== --- cpu/x86/pc/olpc/via/ec-version.fth Sat Apr 30 02:01:18 2011 (r2194) +++ cpu/x86/pc/olpc/via/ec-version.fth Tue May 10 01:27:14 2011 (r2195) @@ -1,5 +1,5 @@ \ The EC microcode -macro: EC_VERSION 2_1_0 +macro: EC_VERSION 2_2_1 \ Alternate command for getting EC microcode, for testing new versions. \ Temporarily uncomment the line and modify the path as necessary Modified: cpu/x86/pc/olpc/via/fw-version.fth ============================================================================== --- cpu/x86/pc/olpc/via/fw-version.fth Sat Apr 30 02:01:18 2011 (r2194) +++ cpu/x86/pc/olpc/via/fw-version.fth Tue May 10 01:27:14 2011 (r2195) @@ -1,3 +1,3 @@ \ The overall firmware revision -macro: FW_MAJOR A -macro: FW_MINOR 65 +macro: FW_MAJOR B +macro: FW_MINOR 03

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openfirmware May 2011