November 2011 - openfirmware - mail.coreboot.org

[commit] r2667 - cpu/x86/pc/olpc
by repository service Nov. 2, 2011

Nov. 2, 2011

Author: quozl Date: Thu Nov 3 00:34:07 2011 New Revision: 2667 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2667 Log: q2e49 Modified: cpu/x86/pc/olpc/versions.fth Modified: cpu/x86/pc/olpc/versions.fth ============================================================================== --- cpu/x86/pc/olpc/versions.fth Thu Nov 3 00:19:13 2011 (r2666) +++ cpu/x86/pc/olpc/versions.fth Thu Nov 3 00:34:07 2011 (r2667) @@ -2,7 +2,7 @@ \ The overall firmware revision macro: FW_MAJOR E -macro: FW_MINOR 48 +macro: FW_MINOR 49 \ The EC microcode macro: EC_VERSION e35

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[commit] r2666 - in cpu/x86/pc/olpc: . via
by repository service Nov. 2, 2011

Nov. 2, 2011

Author: quozl Date: Thu Nov 3 00:19:13 2011 New Revision: 2666 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2666 Log: OLPC XO-1 XO-1.5 - developer local scripting, borrowed from XO-1.75 Modified: cpu/x86/pc/olpc/fw.bth cpu/x86/pc/olpc/via/fw.bth Modified: cpu/x86/pc/olpc/fw.bth ============================================================================== --- cpu/x86/pc/olpc/fw.bth Wed Nov 2 05:43:13 2011 (r2665) +++ cpu/x86/pc/olpc/fw.bth Thu Nov 3 00:19:13 2011 (r2666) @@ -646,6 +646,9 @@ : newrom " flash! http:\\192.168.200.200\new.rom" eval ; : urom " flash! u:\new.rom" eval ; +: qz + " qz" $essid " http:\\qz\" included \ qa test bed scripting, james cameron +; \ Fancy battery charge logger. fload ${BP}/cpu/x86/pc/olpc/charge.fth Modified: cpu/x86/pc/olpc/via/fw.bth ============================================================================== --- cpu/x86/pc/olpc/via/fw.bth Wed Nov 2 05:43:13 2011 (r2665) +++ cpu/x86/pc/olpc/via/fw.bth Thu Nov 3 00:19:13 2011 (r2666) @@ -737,7 +737,9 @@ " flash! http:\\192.168.200.200\new.rom" eval ; : urom enable-serial " flash! u:\new.rom" eval ; -: qrom enable-serial " essid qz" eval " flash http:\\olpc.lan\qrom.rom" eval ; +: qz + " qz" $essid " http:\\qz\" included \ qa test bed scripting, james cameron +; : no-usb-delay " dev /usb false to delay? dend" evaluate ; : null-fsdisk " dev /null : write-blocks-start 3drop ; : write-blocks-finish ; dend" evaluate

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[commit] r2665 - cpu/arm/olpc/1.75
by repository service Nov. 1, 2011

Nov. 1, 2011

Author: quozl Date: Wed Nov 2 05:43:13 2011 New Revision: 2665 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2665 Log: Q4C03 Modified: cpu/arm/olpc/1.75/ec-version.fth cpu/arm/olpc/1.75/fw-version.fth Modified: cpu/arm/olpc/1.75/ec-version.fth ============================================================================== --- cpu/arm/olpc/1.75/ec-version.fth Tue Nov 1 20:35:39 2011 (r2664) +++ cpu/arm/olpc/1.75/ec-version.fth Wed Nov 2 05:43:13 2011 (r2665) @@ -1,5 +1,5 @@ \ The EC microcode -macro: EC_VERSION 4_0_3_02 +macro: EC_VERSION 4_0_3_03 \ Alternate command for getting EC microcode, for testing new versions. \ Temporarily uncomment the line and modify the path as necessary Modified: cpu/arm/olpc/1.75/fw-version.fth ============================================================================== --- cpu/arm/olpc/1.75/fw-version.fth Tue Nov 1 20:35:39 2011 (r2664) +++ cpu/arm/olpc/1.75/fw-version.fth Wed Nov 2 05:43:13 2011 (r2665) @@ -1,3 +1,3 @@ \ The overall firmware revision macro: FW_MAJOR C -macro: FW_MINOR 02 +macro: FW_MINOR 03

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[commit] r2664 - cpu/arm/mmp2
by repository service Nov. 1, 2011

Nov. 1, 2011

Author: wmb Date: Tue Nov 1 20:35:39 2011 New Revision: 2664 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2664 Log: OLPC XO-1.75 - fixed several problems in twsi.fth:set-bus-speed a) Formatting did not conform to the OFW convention (indent pitch 3) b) Missing stack pictures c) Use of "1- 100,000 <" instead of the clearer "100,000 <=" d) Use of and masks instead of clear "invert and" masks e) Incorrect mask values - fields in register are 9 bits, not 8. f) Calculate value for fast SCL instead of hardcoding it (in the wrong bit position) g) Describe the derivation of the dividend values based on working backwards from the default values Modified: cpu/arm/mmp2/twsi.fth Modified: cpu/arm/mmp2/twsi.fth ============================================================================== --- cpu/arm/mmp2/twsi.fth Tue Nov 1 09:04:25 2011 (r2663) +++ cpu/arm/mmp2/twsi.fth Tue Nov 1 20:35:39 2011 (r2664) @@ -179,18 +179,24 @@ : set-bus-standard cr-set h# fffe7fff and to cr-set ; : set-bus-fast cr-set h# fffe7fff and h# 8000 or to cr-set ; -: set-bus-speed ( hz -- ) \ Useful range is 25,000 .. 100,000, or 400,000 - child-address set-twsi-target - dup 1- d# 100,000 < if - set-bus-standard - d# 12,600,000 swap / h# 1ff min h# 7e max - lcr@ h# ffff.ff00 and or lcr! - else - drop - set-bus-fast - lcr@ h# ffff.00ff and h# 0000.1d00 or lcr! - then +\ The dividends below (12,600,000 and 11,600,000) are chosen to give the +\ same values that the LCR defaults to for the data rates 100,000 and 400,000 +\ The TWSI input clock is the 26 MHz VCXO, and the divided value generates +\ both the low phase and the high phase, so you would think that the dividend +\ should be 13,000,000 (half of 26M), but that doesn't give the right result. +\ Perhaps there is an additive factor in the divisor; the manual is quite vague. +: set-bus-speed ( hz -- ) \ Useful range is 25K .. 400K - 100K and 400K are typical + child-address set-twsi-target ( hz ) + dup d# 100,000 <= if ( hz ) + set-bus-standard ( hz ) + d# 12,600,000 swap / h# 1ff min h# 7e max ( divisor ) + lcr@ h# 1ff invert and or lcr! ( ) + else ( hz ) + set-bus-fast ( hz ) + d# 11,600,000 swap / h# 1ff min h# 1d max ( divisor ) + lcr@ h# 3.fe00 invert and swap 9 lshift or lcr! ( ) + then ( ) ; : decode-unit ( adr len -- low high ) parse-2int ; : encode-unit ( low high -- adr len ) >r <# u#s drop [char] , hold r> u#s u#> ;

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[commit] r2663 - cpu/arm/olpc/1.75
by repository service Nov. 1, 2011

Nov. 1, 2011

Author: quozl Date: Tue Nov 1 09:04:25 2011 New Revision: 2663 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2663 Log: OLPC XO-1.75 - use read multiple for acceleration vectors, reducing read time (when data is ready) from 1ms to 600us at 400kHz bus speed. Modified: cpu/arm/olpc/1.75/accelerometer.fth Modified: cpu/arm/olpc/1.75/accelerometer.fth ============================================================================== --- cpu/arm/olpc/1.75/accelerometer.fth Tue Nov 1 09:01:36 2011 (r2662) +++ cpu/arm/olpc/1.75/accelerometer.fth Tue Nov 1 09:04:25 2011 (r2663) @@ -16,9 +16,13 @@ : wext ( b -- n ) dup h# 8000 and if h# ffff0000 or then ; : acceleration@ ( -- x y z ) begin h# 27 acc-reg@ h# 08 and until \ wait for data available - h# 28 acc-reg@ h# 29 acc-reg@ bwjoin wext 5 >>a - h# 2a acc-reg@ h# 2b acc-reg@ bwjoin wext 5 >>a - h# 2c acc-reg@ h# 2d acc-reg@ bwjoin wext 5 >>a + h# 0a8 1 6 " smbus-out-in" $call-parent ( xl xh yl yh zl zh ) + bwjoin wext 5 >>a ( xl xh yl yh z ) + >r ( xl xh yl yh r: z ) + bwjoin wext 5 >>a ( xl xh y r: z ) + >r ( xl xh r: z y ) + bwjoin wext 5 >>a ( x r: z y ) + r> r> ( x y z ) ; : t+ ( x1 y1 z1 x2 y2 z2 -- x3 y3 z3 )

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[commit] r2662 - cpu/arm/mmp2
by repository service Nov. 1, 2011

Nov. 1, 2011

Author: quozl Date: Tue Nov 1 09:01:36 2011 New Revision: 2662 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2662 Log: OLPC XO-1.75 - fix junk on stack after select /accelerometer Modified: cpu/arm/mmp2/twsi.fth Modified: cpu/arm/mmp2/twsi.fth ============================================================================== --- cpu/arm/mmp2/twsi.fth Tue Nov 1 06:37:37 2011 (r2661) +++ cpu/arm/mmp2/twsi.fth Tue Nov 1 09:01:36 2011 (r2662) @@ -186,6 +186,7 @@ d# 12,600,000 swap / h# 1ff min h# 7e max lcr@ h# ffff.ff00 and or lcr! else + drop set-bus-fast lcr@ h# ffff.00ff and h# 0000.1d00 or lcr! then

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[commit] r2661 - cpu/arm/olpc/1.75
by repository service Oct. 31, 2011

Oct. 31, 2011

Author: quozl Date: Tue Nov 1 06:37:37 2011 New Revision: 2661 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2661 Log: OLPC XO-1.75 - wait for data to be available at the accelerometer before reading it. Side effect of doubling test time to five seconds. Removes some positional jitter in roller caused by the low and high bytes being from different samples. Modified: cpu/arm/olpc/1.75/accelerometer.fth Modified: cpu/arm/olpc/1.75/accelerometer.fth ============================================================================== --- cpu/arm/olpc/1.75/accelerometer.fth Tue Nov 1 06:32:03 2011 (r2660) +++ cpu/arm/olpc/1.75/accelerometer.fth Tue Nov 1 06:37:37 2011 (r2661) @@ -15,6 +15,7 @@ : accelerometer-off ( -- ) h# 07 ctl1! ; : wext ( b -- n ) dup h# 8000 and if h# ffff0000 or then ; : acceleration@ ( -- x y z ) + begin h# 27 acc-reg@ h# 08 and until \ wait for data available h# 28 acc-reg@ h# 29 acc-reg@ bwjoin wext 5 >>a h# 2a acc-reg@ h# 2b acc-reg@ bwjoin wext 5 >>a h# 2c acc-reg@ h# 2d acc-reg@ bwjoin wext 5 >>a

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[commit] r2660 - in cpu/arm: mmp2 olpc/1.75
by repository service Oct. 31, 2011

Oct. 31, 2011

Author: quozl Date: Tue Nov 1 06:32:03 2011 New Revision: 2660 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2660 Log: OLPC XO-1.75 - use fast mode (400 kHz i2c) to communicate with new accelerometer. Modified: cpu/arm/mmp2/twsi.fth cpu/arm/olpc/1.75/accelerometer.fth Modified: cpu/arm/mmp2/twsi.fth ============================================================================== --- cpu/arm/mmp2/twsi.fth Tue Nov 1 06:29:32 2011 (r2659) +++ cpu/arm/mmp2/twsi.fth Tue Nov 1 06:32:03 2011 (r2660) @@ -58,13 +58,13 @@ h# 1000 constant BBU_TWSI_TimeOut \ TWSI bus timeout loop counter value -bbu_ICR_IUE bbu_ICR_SCLE or constant iue+scle +bbu_ICR_IUE bbu_ICR_SCLE or value cr-set \ bits to maintain as set : init-twsi-channel ( channel# -- ) set-twsi-channel 7 clock-reg io! 3 clock-reg io! \ Set then clear reset bit 1 us - iue+scle bbu_ICR_UR or cr! \ Reset the unit - iue+scle cr! \ Release the reset + cr-set bbu_ICR_UR or cr! \ Reset the unit + cr-set cr! \ Release the reset 0 sar! \ Set host slave address 0 cr! \ Disable interrupts ; @@ -73,7 +73,7 @@ ; : twsi-run ( extra-flags -- ) - iue+scle or bbu_ICR_TB or cr! ( ) + cr-set or bbu_ICR_TB or cr! ( ) h# 1000 0 do cr@ bbu_ICR_TB and 0= if unloop exit then @@ -94,7 +94,7 @@ bbu_ICR_START twsi-putbyte ( ) sr@ bbu_ISR_BED and if ( ) bbu_ISR_BED sr! ( ) - iue+scle bbu_ICR_MA or cr! ( ) + cr-set bbu_ICR_MA or cr! ( ) true abort" TWSI bus error" then ( ) ; @@ -111,7 +111,7 @@ \ If no result data requested, quit now r@ 0= if ( r: #data-bytes ) r> drop ( ) - iue+scle bbu_ICR_STOP or cr! ( ) + cr-set bbu_ICR_STOP or cr! ( ) exit then ( r: #data-bytes ) then ( r: #data-bytes ) @@ -177,10 +177,19 @@ twsi-out ; -d# 12,600,000 constant numerator -: set-bus-speed ( hz -- ) \ Useful range is currently 25,000 .. 100,000 - child-address set-twsi-target - numerator swap / h# 1ff min h# 7e max lcr! +: set-bus-standard cr-set h# fffe7fff and to cr-set ; +: set-bus-fast cr-set h# fffe7fff and h# 8000 or to cr-set ; +: set-bus-speed ( hz -- ) \ Useful range is 25,000 .. 100,000, or 400,000 + child-address set-twsi-target + dup 1- d# 100,000 < if + set-bus-standard + d# 12,600,000 swap / h# 1ff min h# 7e max + lcr@ h# ffff.ff00 and or lcr! + else + set-bus-fast + lcr@ h# ffff.00ff and h# 0000.1d00 or lcr! + then + ; : decode-unit ( adr len -- low high ) parse-2int ; : encode-unit ( low high -- adr len ) >r <# u#s drop [char] , hold r> u#s u#> ; Modified: cpu/arm/olpc/1.75/accelerometer.fth ============================================================================== --- cpu/arm/olpc/1.75/accelerometer.fth Tue Nov 1 06:29:32 2011 (r2659) +++ cpu/arm/olpc/1.75/accelerometer.fth Tue Nov 1 06:32:03 2011 (r2660) @@ -13,7 +13,6 @@ : ctl4! ( b -- ) h# 23 acc-reg! ; : accelerometer-on ( -- ) h# 47 ctl1! ; : accelerometer-off ( -- ) h# 07 ctl1! ; - : wext ( b -- n ) dup h# 8000 and if h# ffff0000 or then ; : acceleration@ ( -- x y z ) h# 28 acc-reg@ h# 29 acc-reg@ bwjoin wext 5 >>a @@ -49,7 +48,7 @@ : open ( -- flag ) my-unit " set-address" $call-parent bus-speed " set-bus-speed" $call-parent - ['] accelerometer-on catch 0= + ['] accelerometer-on catch 0= ; : close ( -- ) accelerometer-off @@ -122,7 +121,7 @@ average-acceleration@ t- ( dx dy dz ) h# 08 ctl4! ( x y z ) \ High res, Normal mode error? if accelerometer-off true exit then - + accelerometer-off false ; @@ -141,22 +140,22 @@ ['] accelerometer-on catch if \ The attempt to talk at the old address failed, so we assume the new chip \ Support for new LIS3DHTR chip - d# 100,000 to bus-speed - d# 50 to min-x d# 50 to min-y d# 50 to min-z - d# 150 to max-x d# 150 to max-y d# 450 to max-z + d# 400,000 to bus-speed + d# 50 to min-x d# 50 to min-y d# 50 to min-z + d# 150 to max-x d# 150 to max-y d# 450 to max-z h# 32 6 encode-phys " reg" property ['] lis3dhtr-selftest to lis-selftest else accelerometer-off \ Something responded to the old address, so we assume it's the old chip \ Support for old LIS33DE chip - d# 25,000 to bus-speed - d# 20 to min-x d# 20 to min-y d# 20 to min-z - d# 400 to max-x d# 400 to max-y d# 400 to max-z + d# 25,000 to bus-speed + d# 20 to min-x d# 20 to min-y d# 20 to min-z + d# 400 to max-x d# 400 to max-y d# 400 to max-z h# 3a 6 encode-phys " reg" property ['] lis33de-selftest to lis-selftest then -; +; end-package

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[commit] r2659 - cpu/arm/olpc/1.75
by repository service Oct. 31, 2011

Oct. 31, 2011

Author: quozl Date: Tue Nov 1 06:29:32 2011 New Revision: 2659 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2659 Log: OLPC XO-1.75 - split accelerometer debugging code into a separate file. Added: cpu/arm/olpc/1.75/accelerometer.txt Modified: cpu/arm/olpc/1.75/accelerometer.fth Modified: cpu/arm/olpc/1.75/accelerometer.fth ============================================================================== --- cpu/arm/olpc/1.75/accelerometer.fth Mon Oct 31 10:10:14 2011 (r2658) +++ cpu/arm/olpc/1.75/accelerometer.fth Tue Nov 1 06:29:32 2011 (r2659) @@ -14,259 +14,6 @@ : accelerometer-on ( -- ) h# 47 ctl1! ; : accelerometer-off ( -- ) h# 07 ctl1! ; -0 [if] - -select /accelerometer - -: temperature-on ( -- ) h# c0 h# 1f acc-reg! ; -: bdu ( -- ) h# 23 acc-reg@ h# 80 or h# 23 acc-reg! ; -: adc1@ ( -- ) h# 08 acc-reg@ h# 09 acc-reg@ bwjoin wext 5 >>a ; -: adc2@ ( -- ) h# 0a acc-reg@ h# 0b acc-reg@ bwjoin wext 5 >>a ; - -: wait-adc3 begin h# 07 acc-reg@ h# 04 and until ; -: adc3@ ( -- l h ) - h# 0c acc-reg@ h# 0d acc-reg@ bwjoin wext 5 >>a -; -: 1hz ( -- ) h# 20 acc-reg@ h# 0f and h# 10 or h# 20 acc-reg! ; - -: .xr ( n -- ) push-hex 2 .r pop-base space ; -: .dr ( n -- ) push-decimal 3 .r pop-base space ; -: .br ( n -- ) - push-binary 0 <# # # # # [char] . hold # # # # #> type pop-base space ; -: .status-aux h# 07 acc-reg@ .br ; - -: .reg ( register -- value ) - space - dup .xr ." : " ( register ) - acc-reg@ ( value ) - dup .br - dup .xr - dup .dr -; - -: .ureg ( register -- ) - ." " .reg drop -; - -: .regs ( -- ) - h# 07 h# 00 do i .ureg cr loop - - ." STATUS_AUX " h# 07 .reg - dup h# 80 and if ." 321OR " then - dup h# 40 and if ." 3OR " then - dup h# 20 and if ." 2OR " then - dup h# 10 and if ." 1OR " then - dup h# 08 and if ." 321DA " then - dup h# 04 and if ." 3DA " then - dup h# 02 and if ." 2DA " then - dup h# 01 and if ." 1DA " then - drop cr - - ." OUT_1_L " h# 08 .reg cr - ." OUT_1_H " h# 09 .reg - bwjoin wext 5 >>a ." ( " .d ." )" cr - - ." OUT_2_L " h# 0A .reg cr - ." OUT_2_H " h# 0B .reg - bwjoin wext 5 >>a ." ( " .d ." )" cr - - ." OUT_3_L " h# 0C .reg cr - ." OUT_3_H " h# 0D .reg - bwjoin wext 5 >>a ." ( " .d ." )" cr - - ." INT_COUNTER " h# 0E .reg drop cr - ." WHO_AM_I " h# 0F .reg b# 0011.0011 = if ." ok" else ." bad" then cr - - h# 1f h# 10 do i .ureg cr loop - - ." TEMP_CFG_REG " h# 1F .reg - dup h# 80 and if ." ADC_PD " then - dup h# 40 and if ." TEMP_EN " then - dup h# 3f and if ." mbz " then - drop cr - - ." CTRL_REG1 " h# 20 .reg - dup h# f0 and 4 rshift - dup h# 00 = if ." [power-down] " then - dup h# 01 = if ." [1 Hz] " then - dup h# 02 = if ." [10 Hz] " then - dup h# 03 = if ." [25 Hz] " then - dup h# 04 = if ." [50 Hz] " then - dup h# 05 = if ." [100 Hz] " then - dup h# 06 = if ." [200 Hz] " then - dup h# 07 = if ." [400 Hz] " then - dup h# 08 = if ." [1.6 kHz] " then - dup h# 09 = if ." [1.25 kHz / 5 kHz] " then - drop - dup h# 08 and if ." LPen " then - dup h# 04 and if ." Zen " then - dup h# 02 and if ." Yen " then - dup h# 01 and if ." Xen " then - drop cr - - ." CTRL_REG2 " h# 21 .reg - dup h# 80 and if ." HPM1 " then - dup h# 40 and if ." HPM0 " then - dup h# 20 and if ." HPCF2 " then - dup h# 10 and if ." HPCF1 " then - dup h# 08 and if ." FDS " then - dup h# 04 and if ." HPCLICK " then - dup h# 02 and if ." HPIS2 " then - dup h# 01 and if ." HPIS1 " then - drop cr - - ." CTRL_REG3 " h# 22 .reg - dup h# 80 and if ." I1_CLICK " then - dup h# 40 and if ." I1_AOI1 " then - dup h# 20 and if ." I1_AOI2 " then - dup h# 10 and if ." I1_DRDY1 " then - dup h# 08 and if ." I1_DRDY2 " then - dup h# 04 and if ." I1_WTM " then - dup h# 02 and if ." I1_OVERRUN " then - dup h# 01 and if ." rsvd " then - drop cr - - ." CTRL_REG4 " h# 23 .reg - dup h# 80 and if ." BDU " then - dup h# 40 and if ." BLE " then - dup h# 20 and if ." FS1 " then - dup h# 10 and if ." FS2 " then - dup h# 08 and if ." HR " then - dup h# 04 and if ." ST1 " then - dup h# 02 and if ." ST0 " then - dup h# 01 and if ." SIM " then - drop cr - - ." CTRL_REG5 " h# 24 .reg - dup h# 80 and if ." BOOT " then - dup h# 40 and if ." FIFO_EN " then - dup h# 20 and if ." rsvd " then - dup h# 10 and if ." rsvd " then - dup h# 08 and if ." LIR_INT1 " then - dup h# 04 and if ." D4D_INT1 " then - dup h# 02 and if ." mbz " then - dup h# 01 and if ." mbz " then - drop cr - - ." CTRL_REG6 " h# 25 .reg - dup h# 80 and if ." I2_CLICKen " then - dup h# 40 and if ." I2_INT1 " then - dup h# 20 and if ." mbz " then - dup h# 10 and if ." BOOT_I1 " then - dup h# 08 and if ." mbz " then - dup h# 04 and if ." rsvd " then - dup h# 02 and if ." H_LACTIVE " then - dup h# 01 and if ." rsvd " then - drop cr - - ." REFERENCE " h# 26 .reg drop cr - - ." STATUS_REG " h# 27 .reg - dup h# 80 and if ." ZYXOR " then - dup h# 40 and if ." ZOR " then - dup h# 20 and if ." YOR " then - dup h# 10 and if ." XOR " then - dup h# 08 and if ." ZYXDA " then - dup h# 04 and if ." ZDA " then - dup h# 02 and if ." YDA " then - dup h# 01 and if ." ZDA " then - drop cr - - ." OUT_X_L " h# 28 .reg cr - ." OUT_X_H " h# 29 .reg - bwjoin wext 5 >>a ." ( " .d ." )" cr - - ." OUT_Y_L " h# 2a .reg cr - ." OUT_Y_H " h# 2b .reg - bwjoin wext 5 >>a ." ( " .d ." )" cr - - ." OUT_Z_L " h# 2c .reg cr - ." OUT_Z_H " h# 2d .reg - bwjoin wext 5 >>a ." ( " .d ." )" cr - - ." FIFO_CTRL_REG" h# 2e .reg - dup h# 80 and if ." FM1 " then - dup h# 40 and if ." FM0 " then - dup h# 20 and if ." TR " then - dup h# 10 and if ." FTH4 " then - dup h# 08 and if ." FTH3 " then - dup h# 04 and if ." FTH2 " then - dup h# 02 and if ." FTH1 " then - dup h# 01 and if ." FTH0 " then - drop cr - - ." FIFO_SRC_REG " h# 2f .reg - dup h# 80 and if ." WTM " then - dup h# 40 and if ." OVRN_FIFO " then - dup h# 20 and if ." EMPTY " then - dup h# 10 and if ." FSS4 " then - dup h# 08 and if ." FSS3 " then - dup h# 04 and if ." FSS2 " then - dup h# 02 and if ." FSS1 " then - dup h# 01 and if ." FSS0 " then - drop cr - - ." INT1_CFG " h# 30 .reg - dup h# 80 and if ." AOI " then - dup h# 40 and if ." 6D " then - dup h# 20 and if ." ZHIE/ZUPE " then - dup h# 10 and if ." ZLIE/ZDOWNE " then - dup h# 08 and if ." YHIE/YUPE " then - dup h# 04 and if ." YLIE/YDOWNE " then - dup h# 02 and if ." XHIE/XUPE " then - dup h# 01 and if ." XLIE/XDOWNE " then - drop cr - - ." INT1_SRC " h# 31 .reg - dup h# 80 and if ." mbz " then - dup h# 40 and if ." IA " then - dup h# 20 and if ." ZH " then - dup h# 10 and if ." ZL " then - dup h# 08 and if ." YH " then - dup h# 04 and if ." YL " then - dup h# 02 and if ." XH " then - dup h# 01 and if ." XL " then - drop cr - - ." INT1_THS " h# 32 .reg drop cr - ." INT1_DURATION" h# 33 .reg drop cr - - h# 38 h# 34 do i .ureg cr loop - - ." CLICK_CFG " h# 38 .reg - dup h# 80 and if ." rsvd " then - dup h# 40 and if ." rsvd " then - dup h# 20 and if ." ZD " then - dup h# 10 and if ." ZS " then - dup h# 08 and if ." YD " then - dup h# 04 and if ." YS " then - dup h# 02 and if ." XD " then - dup h# 01 and if ." XS " then - drop cr - - ." CLICK_SRC " h# 39 .reg - dup h# 80 and if ." rsvd " then - dup h# 40 and if ." IA " then - dup h# 20 and if ." DCLICK " then - dup h# 10 and if ." SCLICK " then - dup h# 08 and if ." Sign " then - dup h# 04 and if ." Z " then - dup h# 02 and if ." Y " then - dup h# 01 and if ." X " then - drop cr - - ." CLICK_THS " h# 3a .reg drop cr - ." TIME_LIMIT " h# 3b .reg drop cr - ." TIME_LATENCY " h# 3c .reg drop cr - ." TIME_WINDOW " h# 3d .reg drop cr - h# 3e .ureg cr - h# 3f .ureg cr - - \ register decode window is 00-7f, then 80-ff is a mirror -; -[then] - -: bext ( b -- n ) dup h# 80 and if h# ffffff00 or then ; : wext ( b -- n ) dup h# 8000 and if h# ffff0000 or then ; : acceleration@ ( -- x y z ) h# 28 acc-reg@ h# 29 acc-reg@ bwjoin wext 5 >>a Added: cpu/arm/olpc/1.75/accelerometer.txt ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/olpc/1.75/accelerometer.txt Tue Nov 1 06:29:32 2011 (r2659) @@ -0,0 +1,268 @@ +\ accelerometer code for potential future use or debugging + +\ analog to digital converter +: adc1@ ( -- ) h# 08 acc-reg@ h# 09 acc-reg@ bwjoin wext 5 >>a ; +: adc2@ ( -- ) h# 0a acc-reg@ h# 0b acc-reg@ bwjoin wext 5 >>a ; + +\ temperature sensor +: temperature-on ( -- ) h# c0 h# 1f acc-reg! ; +: temperature@ ( -- l h ) + begin h# 07 acc-reg@ h# 04 and until + h# 0c acc-reg@ h# 0d acc-reg@ bwjoin wext 5 >>a +; + +\ block data update +: bdu ( -- ) h# 23 acc-reg@ h# 80 or h# 23 acc-reg! ; + +\ sample rate setting +: odr! ( n -- ) 4 lshift h# 20 acc-reg@ h# 0f and or h# 20 acc-reg! ; + +: 1hz ( -- ) 1 odr! ; +: 10hz ( -- ) 2 odr! ; +: 25hz ( -- ) 3 odr! ; +: 50hz ( -- ) 4 odr! ; \ power up default +: 100hz ( -- ) 5 odr! ; +: 200hz ( -- ) 6 odr! ; +: 400hz ( -- ) 7 odr! ; +: 1.6khz ( -- ) 8 odr! ; +: 5khz ( -- ) 9 odr! ; + +\ sign extend a byte +: bext ( b -- n ) dup h# 80 and if h# ffffff00 or then ; + +\ register dump + +: .xr ( n -- ) push-hex 2 .r pop-base space ; +: .dr ( n -- ) push-decimal 3 .r pop-base space ; +: .br ( n -- ) + push-binary 0 <# # # # # [char] . hold # # # # #> type pop-base space ; + +: .reg ( register -- value ) + space + dup .xr ." : " ( register ) + acc-reg@ ( value ) + dup .br + dup .xr + dup .dr +; + +: .ureg ( register -- ) + ." " .reg drop +; + +: .regs ( -- ) + h# 07 h# 00 do i .ureg cr loop + + ." STATUS_AUX " h# 07 .reg + dup h# 80 and if ." 321OR " then + dup h# 40 and if ." 3OR " then + dup h# 20 and if ." 2OR " then + dup h# 10 and if ." 1OR " then + dup h# 08 and if ." 321DA " then + dup h# 04 and if ." 3DA " then + dup h# 02 and if ." 2DA " then + dup h# 01 and if ." 1DA " then + drop cr + + ." OUT_1_L " h# 08 .reg cr + ." OUT_1_H " h# 09 .reg + bwjoin wext 5 >>a ." ( " .d ." )" cr + + ." OUT_2_L " h# 0A .reg cr + ." OUT_2_H " h# 0B .reg + bwjoin wext 5 >>a ." ( " .d ." )" cr + + ." OUT_3_L " h# 0C .reg cr + ." OUT_3_H " h# 0D .reg + bwjoin wext 5 >>a ." ( " .d ." )" cr + + ." INT_COUNTER " h# 0E .reg drop cr + ." WHO_AM_I " h# 0F .reg b# 0011.0011 = if ." ok" else ." bad" then cr + + h# 1f h# 10 do i .ureg cr loop + + ." TEMP_CFG_REG " h# 1F .reg + dup h# 80 and if ." ADC_PD " then + dup h# 40 and if ." TEMP_EN " then + dup h# 3f and if ." mbz " then + drop cr + + ." CTRL_REG1 " h# 20 .reg + dup h# f0 and 4 rshift + dup h# 00 = if ." [power-down] " then + dup h# 01 = if ." [1 Hz] " then + dup h# 02 = if ." [10 Hz] " then + dup h# 03 = if ." [25 Hz] " then + dup h# 04 = if ." [50 Hz] " then + dup h# 05 = if ." [100 Hz] " then + dup h# 06 = if ." [200 Hz] " then + dup h# 07 = if ." [400 Hz] " then + dup h# 08 = if ." [1.6 kHz] " then + dup h# 09 = if ." [1.25 kHz / 5 kHz] " then + drop + dup h# 08 and if ." LPen " then + dup h# 04 and if ." Zen " then + dup h# 02 and if ." Yen " then + dup h# 01 and if ." Xen " then + drop cr + + ." CTRL_REG2 " h# 21 .reg + dup h# 80 and if ." HPM1 " then + dup h# 40 and if ." HPM0 " then + dup h# 20 and if ." HPCF2 " then + dup h# 10 and if ." HPCF1 " then + dup h# 08 and if ." FDS " then + dup h# 04 and if ." HPCLICK " then + dup h# 02 and if ." HPIS2 " then + dup h# 01 and if ." HPIS1 " then + drop cr + + ." CTRL_REG3 " h# 22 .reg + dup h# 80 and if ." I1_CLICK " then + dup h# 40 and if ." I1_AOI1 " then + dup h# 20 and if ." I1_AOI2 " then + dup h# 10 and if ." I1_DRDY1 " then + dup h# 08 and if ." I1_DRDY2 " then + dup h# 04 and if ." I1_WTM " then + dup h# 02 and if ." I1_OVERRUN " then + dup h# 01 and if ." rsvd " then + drop cr + + ." CTRL_REG4 " h# 23 .reg + dup h# 80 and if ." BDU " then + dup h# 40 and if ." BLE " then + dup h# 20 and if ." FS1 " then + dup h# 10 and if ." FS2 " then + dup h# 08 and if ." HR " then + dup h# 04 and if ." ST1 " then + dup h# 02 and if ." ST0 " then + dup h# 01 and if ." SIM " then + drop cr + + ." CTRL_REG5 " h# 24 .reg + dup h# 80 and if ." BOOT " then + dup h# 40 and if ." FIFO_EN " then + dup h# 20 and if ." rsvd " then + dup h# 10 and if ." rsvd " then + dup h# 08 and if ." LIR_INT1 " then + dup h# 04 and if ." D4D_INT1 " then + dup h# 02 and if ." mbz " then + dup h# 01 and if ." mbz " then + drop cr + + ." CTRL_REG6 " h# 25 .reg + dup h# 80 and if ." I2_CLICKen " then + dup h# 40 and if ." I2_INT1 " then + dup h# 20 and if ." mbz " then + dup h# 10 and if ." BOOT_I1 " then + dup h# 08 and if ." mbz " then + dup h# 04 and if ." rsvd " then + dup h# 02 and if ." H_LACTIVE " then + dup h# 01 and if ." rsvd " then + drop cr + + ." REFERENCE " h# 26 .reg drop cr + + ." STATUS_REG " h# 27 .reg + dup h# 80 and if ." ZYXOR " then + dup h# 40 and if ." ZOR " then + dup h# 20 and if ." YOR " then + dup h# 10 and if ." XOR " then + dup h# 08 and if ." ZYXDA " then + dup h# 04 and if ." ZDA " then + dup h# 02 and if ." YDA " then + dup h# 01 and if ." ZDA " then + drop cr + + ." OUT_X_L " h# 28 .reg cr + ." OUT_X_H " h# 29 .reg + bwjoin wext 5 >>a ." ( " .d ." )" cr + + ." OUT_Y_L " h# 2a .reg cr + ." OUT_Y_H " h# 2b .reg + bwjoin wext 5 >>a ." ( " .d ." )" cr + + ." OUT_Z_L " h# 2c .reg cr + ." OUT_Z_H " h# 2d .reg + bwjoin wext 5 >>a ." ( " .d ." )" cr + + ." FIFO_CTRL_REG" h# 2e .reg + dup h# 80 and if ." FM1 " then + dup h# 40 and if ." FM0 " then + dup h# 20 and if ." TR " then + dup h# 10 and if ." FTH4 " then + dup h# 08 and if ." FTH3 " then + dup h# 04 and if ." FTH2 " then + dup h# 02 and if ." FTH1 " then + dup h# 01 and if ." FTH0 " then + drop cr + + ." FIFO_SRC_REG " h# 2f .reg + dup h# 80 and if ." WTM " then + dup h# 40 and if ." OVRN_FIFO " then + dup h# 20 and if ." EMPTY " then + dup h# 10 and if ." FSS4 " then + dup h# 08 and if ." FSS3 " then + dup h# 04 and if ." FSS2 " then + dup h# 02 and if ." FSS1 " then + dup h# 01 and if ." FSS0 " then + drop cr + + ." INT1_CFG " h# 30 .reg + dup h# 80 and if ." AOI " then + dup h# 40 and if ." 6D " then + dup h# 20 and if ." ZHIE/ZUPE " then + dup h# 10 and if ." ZLIE/ZDOWNE " then + dup h# 08 and if ." YHIE/YUPE " then + dup h# 04 and if ." YLIE/YDOWNE " then + dup h# 02 and if ." XHIE/XUPE " then + dup h# 01 and if ." XLIE/XDOWNE " then + drop cr + + ." INT1_SRC " h# 31 .reg + dup h# 80 and if ." mbz " then + dup h# 40 and if ." IA " then + dup h# 20 and if ." ZH " then + dup h# 10 and if ." ZL " then + dup h# 08 and if ." YH " then + dup h# 04 and if ." YL " then + dup h# 02 and if ." XH " then + dup h# 01 and if ." XL " then + drop cr + + ." INT1_THS " h# 32 .reg drop cr + ." INT1_DURATION" h# 33 .reg drop cr + + h# 38 h# 34 do i .ureg cr loop + + ." CLICK_CFG " h# 38 .reg + dup h# 80 and if ." rsvd " then + dup h# 40 and if ." rsvd " then + dup h# 20 and if ." ZD " then + dup h# 10 and if ." ZS " then + dup h# 08 and if ." YD " then + dup h# 04 and if ." YS " then + dup h# 02 and if ." XD " then + dup h# 01 and if ." XS " then + drop cr + + ." CLICK_SRC " h# 39 .reg + dup h# 80 and if ." rsvd " then + dup h# 40 and if ." IA " then + dup h# 20 and if ." DCLICK " then + dup h# 10 and if ." SCLICK " then + dup h# 08 and if ." Sign " then + dup h# 04 and if ." Z " then + dup h# 02 and if ." Y " then + dup h# 01 and if ." X " then + drop cr + + ." CLICK_THS " h# 3a .reg drop cr + ." TIME_LIMIT " h# 3b .reg drop cr + ." TIME_LATENCY " h# 3c .reg drop cr + ." TIME_WINDOW " h# 3d .reg drop cr + h# 3e .ureg cr + h# 3f .ureg cr + + \ register decode window is 00-7f, msb determines autoincrement +;

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