[OpenBIOS] L2 Cache Settings

Segher Boessenkool segher at kernel.crashing.org
Thu Jan 25 19:38:07 CET 2018

On Thu, Jan 25, 2018 at 11:09:31AM -0500, Jd Lyons wrote:
> Segher, if you have some of the old White Papers on the CPU’s that shipped in Mac’s, or the upgrades offered by third parties, I’d like to get a look at them, if your not under NDA.

You can download this CPU documentation from NPX (who bought it from
FSL, and before it was Motorola).  Those are good docs.

> Would be interesting to know what instructions each supports, and the L2 L3 cache settings and info.

External cache settings needed depend on the board used, the exact cache
chips used, etc.

> Obviously, Open firmware has a entry in the device tree for L2 cache, when I have my Quicksilver I’ll be able to report the L3 cache settings and info in Open Firmware.

L3 is represented exactly like L2 in the device tree.  Settings needed
depend on the system.  For internal caches there usually isn't very
much to configure, so that is much easier.  7447A has internal L2 and
cannot have L3.  But for example older 750 has external L2, and you can
do a whole bunch of settings there (overclock the L2, etc. :-) )


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