[OpenBIOS] L2 Cache Settings

Jd Lyons lyons_dj at yahoo.com
Thu Jan 25 17:09:31 CET 2018



> On Jan 24, 2018, at 1:21 PM, Segher Boessenkool <segher at kernel.crashing.org> wrote:
> 
> On Wed, Jan 24, 2018 at 09:47:13AM -0500, Programmingkid wrote:
>>> On Jan 23, 2018, at 4:57 PM, Segher Boessenkool <segher at kernel.crashing.org> wrote:
>>> You meant something like
>>> 
>>> void enable_L2_7447A(void)
>>> {
>>> 	asm("mtspr %0,%1" : : "n"(1017), "r"(0x80000000));
>>> }
>> 
>> I would change "asm" to "asm volatile" to prevent the compiler from optimizing this code out. 
> 
> The asm has no outputs so it is already volatile.
> 
> 
> Segher
> 
> -- 
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Segher, if you have some of the old White Papers on the CPU’s that shipped in Mac’s, or the upgrades offered by third parties, I’d like to get a look at them, if your not under NDA.

Would be interesting to know what instructions each supports, and the L2 L3 cache settings and info.

It’s not clear to me what qemu-system-ppc emulates, surely the L1 cache.

Obviously, Open firmware has a entry in the device tree for L2 cache, when I have my Quicksilver I’ll be able to report the L3 cache settings and info in Open Firmware.

So if we can figure out a graceful way of adding a correct entry on the device tree in Open Bios for the L2/L3 cache, that would be optimal.   


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