[OpenBIOS] L2 Cache Settings

Jd Lyons lyons_dj at yahoo.com
Fri Jan 26 11:04:02 CET 2018

> On Jan 25, 2018, at 1:38 PM, Segher Boessenkool <segher at kernel.crashing.org> wrote:
> On Thu, Jan 25, 2018 at 11:09:31AM -0500, Jd Lyons wrote:
>> Segher, if you have some of the old White Papers on the CPU’s that shipped in Mac’s, or the upgrades offered by third parties, I’d like to get a look at them, if your not under NDA.
> You can download this CPU documentation from NPX (who bought it from
> FSL, and before it was Motorola).  Those are good docs.

Thanks, I did a few half hearted google searches, that didn’t yield the docs, I figured they we still around somewhere. Sometimes goole is obtuse, it’s like the computer from the Hitchhikers Guide, it matters how you ask the question.

>> Would be interesting to know what instructions each supports, and the L2 L3 cache settings and info.
> External cache settings needed depend on the board used, the exact cache
> chips used, etc.
>> Obviously, Open firmware has a entry in the device tree for L2 cache, when I have my Quicksilver I’ll be able to report the L3 cache settings and info in Open Firmware.
> L3 is represented exactly like L2 in the device tree.  Settings needed
> depend on the system.  For internal caches there usually isn't very
> much to configure, so that is much easier.  7447A has internal L2 and
> cannot have L3.  But for example older 750 has external L2, and you can
> do a whole bunch of settings there (overclock the L2, etc. :-) )
> Segher

I wonder, in specific to emulating caches if that yields any performance increase. Just as a layman, I have a basic understanding of cpu’s and some understanding of caches. I remember having an old Powermac 8600 with a Sonnet G3 450, having the L2 cache enabled and overclocking it within the constraints of the ram used for the external cache could yield some very worthwhile performance increase.

I’m collecting some of these old PPC Mac’s while they are dirt cheap, before people just toss the on the scrap heap because no one want to pay the shipping, mainly to try and make qemu a better ppc emulator, as no matter how well built some of this old hardware was, it will all fail given enough time and is limited to the physical constraints of the components used. Of course the goal for me is running old software, things like the earlier versions of iMovie that weren’t so complex as to confuse the user with feature bloat.

With an emulated cpu, we’re only really limited to how well the code is written to take advantage of the host cpu. 32 bit PPC is never going to get any faster, baring as unforeseen reality, but x86 and arm continue to push Moore’s Law, so running PPC in emulation will continue to see performance increases for software that is limited to clock cycles.

With qemu-ppc I find the integer performance very well maintained, it seems to scale well with the host cpu, tho the FPU and the Vec units are woeful and need a lot of work. Sheepshaver hands down outperforms qemu in FPU and Vec calculations, tho the code just became unmaintainable to the developers, or so I’ve been told. I’ve looked at it, to see if any of the code could be ported to qemu to help increase FPU and Vec and the code seems spread all over the place, and it’s hard to figure how all the pieces fit together.  

It seems like it could be a challenge to emulate caches, I’ll have to dig deeper into qemu and see how the issue is dealt with. 

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