[OpenBIOS] Re: Status

Konstantin Zhidkov kzhidkov at avia.formoza.ru
Fri Mar 17 20:05:25 CET 2000

The APICBASE MSR is described in Intel Architecture Software Developer's
Manual,Volume 3,
which is available from developer.intel.com. This MSR controls CPU's
local APIC,
which should be disabled, if we coming to use 8259. Correct code for this

    mov ecx, 0x1b  ; APICBASE MSR
    and eax, ~0x800  ; clear APIC Global Enable Bit

I added this code as I686_INIT macro in boot/boot16/ia32.inc, and timer
ticks counter become
working on my i810 MB. Of course, this fix will not work in
multiprocessor environment --
in such case we have to perform full APIC initialization procedure.

Sorry for bad english.


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