[OpenBIOS] Re: Status

Ronald G. Minnich rminnich at lanl.gov
Mon Mar 20 21:45:13 CET 2000

On Fri, 17 Mar 2000, Konstantin Zhidkov wrote:
> There is APICBASE MSR int P6 processors,which should be initialized
> before first interrupt occur. Here is simplest working code:
> xor eax, eax
> xor edx, edx
> mov ecx, 0x1b
> wrmsr

This did the trick for me, BTW. Interrupts happened, Jiffies incremented,
calibrate_delay() finished ...


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