[OpenBIOS] Re: Status

[Ronald G. Minnich]

On Fri, 17 Mar 2000, Konstantin Zhidkov wrote:

> There is APICBASE MSR int P6 processors,which should be initialized
> before first interrupt occur. Here is simplest working code:
> 
> xor eax, eax
> xor edx, edx
> mov ecx, 0x1b
> wrmsr
> 

I will try this. Can you tell us more about what is going on with this
operation? I don't have good enough documentation I think. 

Thanks

ron

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