[flashrom] Failing to WRITE an eeprom image to an "SST25VF512(A)" eeprom using a Bus Pirate (under Linux)

[Adam Ward]

(Flashrom Logfile attached)

I'm having great difficulty performing a "-w" operation on an SST25VF512(A)
chip using my Bus Pirate under Linux.

My hardware is as follows:
A brand new EEPROM (fresh from the tube) is *carefully* soldered onto a SMD
SOIC8 breakout board / programming harness I made, the ribbon going to the
bus pirate is less than 80mm long.  There is a 0.1 uF decoupling ceramic
cap very close to the power pins on the IC.  I have verified that the IC is
receiving 3.3 V from the Bus Pirate.  There are no shorts or stray flying
wires anywhere.  I have tried turning the speed all the way down to
"spispeed=30k" and the behaviour is the same.  I believe the pinouts are
all correct as it looks like the flashrom program can read data from the
chips.

I have tried 3 separate EEPROM chips (all the same type) just in cast I had
exceeded the write endurance of the silicon.  They all fail in the same way
but one of them managed to get to the 5th block before it hanged.

The log file I have attached just stops at the last line and never gets any
further.

Can someone suggest a reason for this failure?  I really need to get this
working.  I can provide photos of the setup if that would help.


Adam
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/flashrom/attachments/20181019/9e8817f7/attachment.html>
-------------- next part --------------
tail: log: file truncated
flashrom v0.9.9-r1954 on Linux 4.17.10 (x86_64)
flashrom was built with libpci 3.5.2, GCC 6.3.0 20170221, little endian
Command line (8 args): flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=250k -c SST25VF512(A) -w sernum_eeprom -o log
Calibrating delay loop... OS timer resolution is 1 usecs, 2792M loops per second, 10 myus = 11 us, 100 myus = 122 us, 1000 myus = 1030 us, 10000 myus = 10032 us, 4 myus = 4 us, OK.
Initializing buspirate_spi programmer
Detected Bus Pirate hardware v3a
Detected Bus Pirate firmware 5.10 ("v5.10")
Using SPI command set v2.
SPI speed is 250kHz
Raw bitbang mode version 1
Raw SPI mode version 1
The following protocols are supported: SPI.
Probing for SST SST25VF512(A), 64 kB: probe_spi_rems: id1 0xbf, id2 0x48
Found SST flash chip "SST25VF512(A)" (64 kB, SPI) on buspirate_spi.
Chip status register is 0x0c.
Chip status register: Block Protect Write Disable (BPL) is not set
Chip status register: Auto Address Increment Programming (AAI) is not set
Chip status register: Block Protect 3 (BP3) is not set
Chip status register: Block Protect 2 (BP2) is not set
Chip status register: Block Protect 1 (BP1) is set
Chip status register: Block Protect 0 (BP0) is set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Some block protection in effect, disabling... disabled.
Reading old flash chip contents... done.
Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EW