[flashrom] [PATCH] Try to handle non-x86 sanely

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Fri Mar 26 01:51:32 CET 2010


flashrom is very x86 centric. It does work on other architectures if you
get it to compile. Try to fix the worst compile errors on non-x86 for a
full build.

Should work in theory with a default build if you exclude nic3com.
Will pretty sure break compilation on Alpha.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-ioport_x86_only/hwaccess.c
===================================================================
--- flashrom-ioport_x86_only/hwaccess.c	(Revision 984)
+++ flashrom-ioport_x86_only/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,8 @@
 #include <errno.h>
 #include "flash.h"
 
+#if defined(__i386__) || defined(__x86_64__)
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,6 +56,22 @@
 #endif
 }
 
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+void get_io_perms(void)
+{
+}
+
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 #ifdef __DJGPP__
 
 extern unsigned short  segFS;
Index: flashrom-ioport_x86_only/hwaccess.h
===================================================================
--- flashrom-ioport_x86_only/hwaccess.h	(Revision 984)
+++ flashrom-ioport_x86_only/hwaccess.h	(Arbeitskopie)
@@ -31,6 +31,8 @@
 #include <pci/pci.h>
 #endif
 
+#if defined(__i386__) || defined(__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +164,11 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif
 
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+/* Port I/O is not available on PowerPC. */
+
+#else
+#error Unknown architecture
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-ioport_x86_only/it87spi.c
===================================================================
--- flashrom-ioport_x86_only/it87spi.c	(Revision 984)
+++ flashrom-ioport_x86_only/it87spi.c	(Arbeitskopie)
@@ -29,6 +29,8 @@
 #include "chipdrivers.h"
 #include "spi.h"
 
+#if defined(__i386__) || defined(__x86_64__)
+
 #define ITE_SUPERIO_PORT1	0x2e
 #define ITE_SUPERIO_PORT2	0x4e
 
@@ -347,3 +349,5 @@
 
 	return 0;
 }
+
+#endif
Index: flashrom-ioport_x86_only/physmap.c
===================================================================
--- flashrom-ioport_x86_only/physmap.c	(Revision 984)
+++ flashrom-ioport_x86_only/physmap.c	(Arbeitskopie)
@@ -238,6 +238,8 @@
 	return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }
 
+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -455,4 +457,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-ioport_x86_only/nic3com.c
===================================================================
--- flashrom-ioport_x86_only/nic3com.c	(Revision 984)
+++ flashrom-ioport_x86_only/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"
 
+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
 	OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
 	return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unknown architecture
+#endif
Index: flashrom-ioport_x86_only/wbsio_spi.c
===================================================================
--- flashrom-ioport_x86_only/wbsio_spi.c	(Revision 984)
+++ flashrom-ioport_x86_only/wbsio_spi.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include "chipdrivers.h"
 #include "spi.h"
 
+#if defined(__i386__) || defined(__x86_64__)
+
 #define WBSIO_PORT1	0x2e
 #define WBSIO_PORT2	0x4e
 
@@ -199,3 +201,5 @@
 
 	return spi_chip_write_1(flash, buf);
 }
+
+#endif
Index: flashrom-ioport_x86_only/chipset_enable.c
===================================================================
--- flashrom-ioport_x86_only/chipset_enable.c	(Revision 984)
+++ flashrom-ioport_x86_only/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"
 
+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;
 
 static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
 	return 0;
 }
 
+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
 	{0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
 	{0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
 	{0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1417,7 +1422,7 @@
 	{0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
 	{0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
 	{0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
 	{},
 };
 
Index: flashrom-ioport_x86_only/board_enable.c
===================================================================
--- flashrom-ioport_x86_only/board_enable.c	(Revision 984)
+++ flashrom-ioport_x86_only/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"
 
+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1299,6 +1300,8 @@
 	return it8712f_gpio_set(32, 1);
 }
 
+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1342,6 +1345,7 @@
 struct board_pciid_enable board_pciid_enables[] = {
 
 	/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
 	{0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
 	{0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
 	{0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1407,7 +1411,7 @@
 	{0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
 	{0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
 	{0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
 	{     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };
 


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