[flashrom] [PATCH] Fix erase-blocks specification for the Atmel AT49F002(N)(T)

Uwe Hermann uwe at hermann-uwe.de
Sat Jan 23 23:03:49 CET 2010

On Sat, Jan 23, 2010 at 07:53:44PM +0100, Carl-Daniel Hailfinger wrote:
> Yes, that's expected. Verbose mode will tell you that flashrom does a
> fallback to whole-chip erase after the sector erase fails.

Hm, that should also be printed in non-verbose then, IMHO.

> >From my datasheet:
>  SA = sector addresses:
>  For the AT49F002(N):
>  SA = 00000 to 03FFF for BOOT BLOCK
>  Nothing will happen and the device goes back to the read mode in 100 ns
>  SA = 04000 to 05FFF for PARAMETER BLOCK 1
>  SA = 06000 to 07FFF for PARAMETER BLOCK 2
>  SA = 08000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 1
>  This command will erase - PB1, PB2 and MMB1
>  SA = 20000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 2
> That looks like a 16k, 8k, 8k, 96k, 128k layout (starting at lowest
> address).
> Can you tell us where you saw 64k eraseblocks in the datasheet? I looked
> at http://www.atmel.com/dyn/resources/prod_documents/DOC1017.PDF and
> didn't see any 64k eraseblocks in there.

Yeah, we talked about this on IRC, and it turns out there are various
AT49* chips with the same IDs. "Luckily" they seem to have an
"additional device code" field we can query which hopefully allows us to
differ between the chips. See
  http://atmel.com/dyn/products/product_card.asp?part_id=3076, page 14
for the ID mechanism. This datasheet is also what I looked at for the
chip, which has the block layout I posted in my patch.

If nobody beats me to it I'll post a patch for handling all of these
chips properly.

> Then again, this chip is crazy anyway. It seems that if you erase the
> Main Memory Array Block 1 it affects the Parameter Blocks as well. If
> that is true, we have a big problem because the address of the erase
> command does not correspond with the erased block anymore and we should
> tar and feather the hw designer. Put differently, if you do a
> block-by-block erase/write, a later erase (MMB1) will kill earlier
> writes (PB1/PB2).

Hm, does this make more sense if looking at the datasheet I posted?

> > Oh, one question -- is the order of erase-blocks as specified in
> > flashchips.c relevant? AT49F002(N) and AT49F002(N)T have different
> > orders right now.
> Yes, the eraseblocks are listed as starting from the lowest address. A
> top boot block device will therefore start with big eraseblocks (bottom
> of flash) and end with small eraseblocks (top of flash).

Ah, yes. Makes sense, thanks!

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