[flashrom] [commit] r913 - trunk

[repository service]

Author: mkarcher
Date: Thu Feb 25 12:38:23 2010
New Revision: 913
URL: http://flashrom.org/trac/coreboot/changeset/913

Log:
Rename identifiers called 'byte'

Still fallout of adding "-Wshadow". Missed the ht1000 one
(chipset_enable is not compied on Windows where we had the collision
with "byte" last time) and the other occurrence is newly introduced.
Old libpci defines a global symbol called "byte" too.

Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Modified:
   trunk/chipset_enable.c

Modified: trunk/chipset_enable.c
==============================================================================
--- trunk/chipset_enable.c	Wed Feb 24 23:43:44 2010	(r912)
+++ trunk/chipset_enable.c	Thu Feb 25 12:38:23 2010	(r913)
@@ -1060,7 +1060,7 @@
 static int enable_flash_mcp6x_7x_common(struct pci_dev *dev, const char *name)
 {
 	int ret = 0;
-	uint8_t byte;
+	uint8_t val;
 	uint16_t status;
 	char *busname;
 	uint32_t mcp_spibaraddr;
@@ -1070,10 +1070,10 @@
 	msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
 
 	/* dev is the ISA bridge. No idea what the stuff below does. */
-	byte = pci_read_byte(dev, 0x8a);
+	val = pci_read_byte(dev, 0x8a);
 	msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
-		 "is %i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
-	switch ((byte >> 5) & 0x3) {
+		 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
+	switch ((val >> 5) & 0x3) {
 	case 0x0:
 		buses_supported = CHIP_BUSTYPE_LPC;
 		break;
@@ -1090,9 +1090,9 @@
 
 	/* Force enable SPI and disable LPC? Not a good idea. */
 #if 0
-	byte |= (1 << 6);
-	byte &= ~(1 << 5);
-	pci_write_byte(dev, 0x8a, byte);
+	val |= (1 << 6);
+	val &= ~(1 << 5);
+	pci_write_byte(dev, 0x8a, val);
 #endif
 
 	/* Look for the SMBus device (SMBus PCI class) */
@@ -1224,16 +1224,16 @@
 
 static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
 {
-	uint8_t byte;
+	uint8_t val;
 
 	/* Set the 4MB enable bit. */
-	byte = pci_read_byte(dev, 0x41);
-	byte |= 0x0e;
-	pci_write_byte(dev, 0x41, byte);
-
-	byte = pci_read_byte(dev, 0x43);
-	byte |= (1 << 4);
-	pci_write_byte(dev, 0x43, byte);
+	val = pci_read_byte(dev, 0x41);
+	val |= 0x0e;
+	pci_write_byte(dev, 0x41, val);
+
+	val = pci_read_byte(dev, 0x43);
+	val |= (1 << 4);
+	pci_write_byte(dev, 0x43, val);
 
 	return 0;
 }