[coreboot] Kabylake unable to boot with post code 0x71 "SGX: pre-conditions not met"

[Jose Trujillo]

Dear Naresh,

I choose the RVP8 board because is the only match in terms of CPU and memory, other templates made by google supports kabylake U/Y only processors and no DDR4.

My system has differences and I will check them after I finish GPIO.

I already determined the proper VR settings and set them in devicetree (the default voltage setting was 0V -power was shutdown??-) and I will see if after the corrections of VR and GPIO the system boots.

I will follow your advise of checking EC and about the base FW I am using the original UEFI AMI FW but, if still doesn't boot I will replace ME and descriptor as you suggested.

Thank you,
Jose Trujillo.

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Thursday, September 20, 2018 4:03 PM, Naresh G. Solanki <naresh.solanki.2011 at gmail.com> wrote:

> RVP8 is known to boot. GPIO config should be fine unless you are modifying HW.
>
> In logs you provided, ec communication seems to fail. Thus can you
> make sure right EC is flashed in the RVP8.
> In my board, it looks like this:
> recv_ec_data: 0x10
> recv_ec_data: 0x69
>
> Also make sure that you have right descriptor & ME are for RVP8
>
> Attached is config I've tried & it executed till end of ramstage.
>
> On Thu, Sep 20, 2018 at 1:25 PM Jose Trujillo via coreboot
> coreboot at coreboot.org wrote:
>
> > Hello Nico,
> > Yes, I am using Intel Kabylake DDR4 RVP8 board.
> >
> > > Never use another board's GPIO settings.
> > > Reading the mail list yesterday I saw that warning maybe from you and I will do the correct changes to GPIO just after editing VR settings.
> >
> > I am just started coreboot several months ago and there is still a lot of road to go for me and still don't understand many things; but I am doing my best to get aligned with the coreboot project.
> > After the GPIO changes I will check my schematics to check for hardware differences before I flash it into my device.
> > Thank you ALL for your help.
> > Jose Trujillo
> > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > On Wednesday, September 19, 2018 10:15 PM, Nico Huber nico.h at gmx.de wrote:
> >
> > > Hi Jose,
> > > On 12.09.2018 15:12, Jose Trujillo via coreboot wrote:
> > >
> > > > To begin with the system didn't find memory attached...
> > > > but there is memory attached, SPD address mismatch? I will check.
> > > > ....
> > > > .......Timeout while sending command 0x0d to EC!
> > >
> > > I'm not sure what this is about. Did you try to talk to your board's
> > > EC? Can you share the code? Or do you run another board's code on your
> > > board? That would explain why things go wrong. Also, my usual warning:
> > > Never use another board's GPIO settings.
> > > Nico
> >
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > https://mail.coreboot.org/mailman/listinfo/coreboot
>
> --
>
> Best regards,
> Naresh G. Solanki