[coreboot] Kabylake unable to boot with post code 0x71 "SGX: pre-conditions not met"

[Naresh G. Solanki]

RVP8 is known to boot. GPIO config should be fine unless you are modifying HW.

In logs you provided, ec communication seems to fail. Thus can you
make sure right EC is flashed in the RVP8.
In my board, it looks like this:
recv_ec_data: 0x10
recv_ec_data: 0x69

Also make sure that you have right descriptor & ME are for RVP8

Attached is config I've tried & it executed till end of ramstage.



On Thu, Sep 20, 2018 at 1:25 PM Jose Trujillo via coreboot
<coreboot at coreboot.org> wrote:
>
> Hello Nico,
>
> Yes, I am using Intel Kabylake DDR4 RVP8 board.
>
> > Never use another board's GPIO settings.
> Reading the mail list yesterday I saw that warning maybe from you and I will do the correct changes to GPIO just after editing VR settings.
>
> I am just started coreboot several months ago and there is still a lot of road to go for me and still don't understand many things; but I am doing my best to get aligned with the coreboot project.
>
> After the GPIO changes I will check my schematics to check for hardware differences before I flash it into my device.
>
> Thank you ALL for your help.
> Jose Trujillo
>
> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> On Wednesday, September 19, 2018 10:15 PM, Nico Huber <nico.h at gmx.de> wrote:
>
> > Hi Jose,
> >
> > On 12.09.2018 15:12, Jose Trujillo via coreboot wrote:
> >
> > > To begin with the system didn't find memory attached...
> > > but there is memory attached, SPD address mismatch? I will check.
> > > ....
> > > .......Timeout while sending command 0x0d to EC!
> >
> > I'm not sure what this is about. Did you try to talk to your board's
> > EC? Can you share the code? Or do you run another board's code on your
> > board? That would explain why things go wrong. Also, my usual warning:
> > Never use another board's GPIO settings.
> >
> > Nico
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot



-- 
Best regards,
Naresh G. Solanki
-------------- next part --------------
CONFIG_CCACHE=y
CONFIG_VENDOR_INTEL=y
CONFIG_CBFS_SIZE=0x300000
CONFIG_HAVE_IFD_BIN=y
CONFIG_HAVE_ME_BIN=y
# CONFIG_POST_DEVICE is not set
CONFIG_BOARD_INTEL_KBLRVP8=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/fsp/fspm.bin"
CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/fsp/fsps.bin"
CONFIG_CPU_MICROCODE_HEADER_FILES="3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/microcode/microcode_blob.h"
# CONFIG_CONSOLE_CBMEM is not set
CONFIG_UART_PCI_ADDR=0x82072000
# CONFIG_SKIP_FSP_CAR is not set
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y
CONFIG_RUN_FSP_GOP=y
CONFIG_FSP_M_XIP=y
CONFIG_LPC_TPM=y
# CONFIG_SQUELCH_EARLY_SMP is not set
CONFIG_CONSOLE_POST=y
CONFIG_PAYLOAD_NONE=y