[coreboot] Kabylake unable to boot with post code 0x71

Tue Sep 18 11:30:08 CEST 2018

Dear Naresh / All:

I added their corresponding FSP headers but still the system never returns from the FSP function (fsp_silicon_init) post 0x71.

My question is if somebody can tell me how to enable (if possible) FSP port 80 post codes and/or FSP serial debug from SIO (non SOC) UART.

Thank you,
Jose Trujillo

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Monday, September 17, 2018 6:14 PM, Naresh G. Solanki <naresh.solanki.2011 at gmail.com> wrote:

> Location in coreboot folder:
> https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/skykabylake
>
> Header Files can be taken from location:
> https://github.com/IntelFsp/FSP/tree/master/KabylakeFspBinPkg/Include
>
> FSP binary can be taken from:
> https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Fsp.fd
>
> This file needs to be split into fspm.bin fsps.bin . For this refer:
> https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/UserManuals/SplitFspBinUserManual.md
> On Mon, Sep 17, 2018 at 7:51 PM Jose Trujillo ce.autom at protonmail.com wrote:
>
> > Thank you Naresh,
> > How to do the copy?
> > Could you give me some details?
> > You too have an excellent day.
> > Jose.
> > Sent with ProtonMail Secure Email.
> > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > On Monday, September 17, 2018 5:17 PM, Naresh G. Solanki naresh.solanki.2011 at gmail.com wrote:
> > I guess the FSP version you have is 3.5.0
> > You should have received fsp header along with fsp binary in single package.
> > However you can get FSP binaries and header from https://github.com/IntelFsp/FSP
> > Also make sure you copy FSP header version equal fsp binary version.
> > All the best!
> > On Mon 17 Sep, 2018, 3:34 PM Jose Trujillo via coreboot, coreboot at coreboot.org wrote:
> >
> > > Dear Naresh:
> > > You are right; it never returns from the FSP function (fsp_silicon_init).
> > > chip_fsp20.c Ln.169
> > > void soc_init_pre_device(void chip_info)
> > > {
> > > printk(BIOS_INFO, "Entering: fsp_silicon_init"); // Added
> > > / Perform silicon specific init. /
> > > fsp_silicon_init(romstage_handoff_is_resume());
> > > / swap enabled PCI ports in device tree if needed */printk(BIOS_INFO, "Entering: pcie_override_devicetree"); // Added
> > > pcie_override_devicetree_after_silicon_init();
> > > printk(BIOS_INFO, "Exit: soc_init_pre_device"); // Added
> > > }
> > > Serial dump.
> > > ....
> > > Enabling SMIs.
> > > Locking SMM.
> > > VMX : param.enable = 0
> > > VMX: pre-conditions not met
> > > VMX: pre-conditions not met
> > > VMX: pre-conditions not met
> > > SGX: pre-conditions not met
> > > VMX: pre-conditions not met
> > > SGX: pre-conditions not met
> > > POST: 0x71
> > > SGX: pre-conditions not met
> > > SGX: pre-conditions not met
> > > Entering: fsp_silicon_init <------ never returns from FSP.
> > > ....
> > > About the FSP header version I am not sure how exactly to obtain it but getting the binary decription from BCT I got:
> > > Header Revision: 0x3
> > > Image Revision: 0x3050000
> > > 3.0.5 ????
> > > See the attached file for more details about the FSP binary.
> > > Please advise.
> > > Thank you,
> > > Jose Trujillo.
> > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > > On Friday, September 14, 2018 6:58 PM, Naresh G. Solanki naresh.solanki.2011 at gmail.com wrote:
> > >
> > > > With available data. It is most likely that it might have stuck
> > > > somewhere in function
> > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/chip_fsp20.c#n169
> > > > You can add printk in that function & other functions called by it to
> > > > bisect & confirm the exact position of hang..
> > > > Also can you please check FSP binary version you are using versus FSP
> > > > header version checked-out in coreboot(which is currently 2.9.2).
> > > > They should be
> > > > On Fri, Sep 14, 2018 at 7:55 PM Jose Trujillo via coreboot
> > > > coreboot at coreboot.org wrote:
> > > >
> > > > > Here is Naresh....
> > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > > > > On Friday, September 14, 2018 4:49 PM, Naresh G. Solanki naresh.solanki.2011 at gmail.com wrote:
> > > > > Can you also provide latest complete log.
> > > > > On Fri 14 Sep, 2018, 2:10 PM Jose Trujillo via coreboot, coreboot at coreboot.org wrote:
> > > > >
> > > > > > Thank you Naresh,
> > > > > > I added the missing PCH device id following your advise, also enabled DEBUG_BOOT_STATE but I am still not able to get more information via serial debug about the exact location of the problem (but now I am certain is in the coreboot code not in FSP).
> > > > > > I suspect the code involved aound this issue is hardwaremain.c and device.c....
> > > > > > Only the first "boot" just after flash I notice that the ethernet and SATA LEDs blink for a fraction of a second then reboots.
> > > > > > After that, the following attempts to boot I don't see LED activity neither reboots, just halted in some kind of loop.
> > > > > > According to the serial dump the las printed text is "0x71" but my question is if the serial port gets broken still during "BS_DEV_INIT_CHIPS" or is already doing "BS_DEV_ENUMERATE".
> > > > > > As Naresh pointed my PCH H chipset "Kabylake-H HM175" was not added to the list; I added it but may be is needed to do something else to make it work.
> > > > > > Or istill is misconfigured (attached my .config file for your review)... I someone has a similar system working and want to share its configuration files to compare them myself I will be grateful.
> > > > > > Jose Trujillo.
> > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > > > > > On Wednesday, 12 September 2018 19:33, Naresh G. Solanki naresh.solanki.2011 at gmail.com wrote:
> > > > > > Hi
> > > > > >
> > > > > > > PCH: device id a152 (rev 31) is Unknown
> > > > > >
> > > > > > This indicates that LPCID 0xa152 is not added.
> > > > > > The #define should be added in source path: https://review.coreboot.org/cgit/coreboot.git/tree/src/include/device/pci_ids.h#n2721
> > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/block/lpc/lpc.c#n131
> > > > > > &
> > > > > > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/bootblock/report_platform.c#n73
> > > > > > as well.
> > > > > > Additionally you can enable config DEBUG_BOOT_STATE to understand where exactly its stuck.
> > > > > > Regards,
> > > > > > Naresh G. Solanki
> > > > > > On Wed, Sep 12, 2018 at 9:24 PM Jose Trujillo via coreboot coreboot at coreboot.org wrote:
> > > > > >
> > > > > > > Dear All,
> > > > > > > About the memory I just changed the dimm to address A0 and now coreboot is reporting correctly 1 dimm detected.
> > > > > > > But still no luck on the 0x71 post code loop (looks it is in some kind of loop because is still responsive to power and reset buttons).
> > > > > > > I don't know where this loop could be located (coreboot or FSP).
> > > > > > > The description on the post_codes.h file shows the following:
> > > > > > > ....
> > > > > > > /**
> > > > > > >
> > > > > > > -   \brief Initializing Chips
> > > > > > > -
> > > > > > > -   Boot State Machine: bs_dev_init_chips()
> > > > > > >     */
> > > > > > >     #define POST_BS_DEV_INIT_CHIPS 0x71
> > > > > > >     ....
> > > > > > >
> > > > > > >
> > > > > > > Any advice on this issue?
> > > > > > > Attached is the serial dump with extra information.
> > > > > > > Thank you
> > > > > > > Jose Trujillo
> > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > > > > > > On Wednesday, 12 September 2018 16:12, Jose Trujillo ce.autom at protonmail.com wrote:
> > > > > > > To begin with the system didn't find memory attached...
> > > > > > > but there is memory attached, SPD address mismatch? I will check.
> > > > > > > ....
> > > > > > > .......Timeout while sending command 0x0d to EC!
> > > > > > > recv_ec_data: 0xff
> > > > > > > recv_ec_data: 0xff
> > > > > > > SPD index 7
> > > > > > > No memory dimm at address A0
> > > > > > > No memory dimm at address A2
> > > > > > > No memory dimm at address A6
> > > > > > > ....
> > > > > > > 0 DIMMs found
> > > > > > > ....
> > > > > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > > > > > > On Wednesday, 12 September 2018 13:29, Jose Trujillo via coreboot coreboot at coreboot.org wrote:
> > > > > > > Dear coreboot engineers:
> > > > > > > Right now I am stuck with a Kabylake system with the following message:
> > > > > > > ....
> > > > > > > CPU #1 initialized
> > > > > > > apic_id: 0x06 done.
> > > > > > > microcode: updated to revision 0x8d date=2018-01-21
> > > > > > > CPU #3 initialized
> > > > > > > bsp_do_flight_plan done after 220 msecs.
> > > > > > > CPU: frequency set to 3600 MHz
> > > > > > > Enabling SMIs.
> > > > > > > Locking SMM.
> > > > > > > VMX : param.enable = 0
> > > > > > > VMX: pre-conditions not met
> > > > > > > SGX: pre-conditions not met
> > > > > > > VMX: pre-conditions not met
> > > > > > > VMX: pre-conditions not met
> > > > > > > SGX: pre-conditions not met
> > > > > > > SGX: pre-conditions not met
> > > > > > > VMX: pre-conditions not met
> > > > > > > SGX: pre-conditions not met
> > > > > > > POST: 0x71
> > > > > > > ....
> > > > > > > May be some configuration is missing and I am trying to find this out myself but if someone of you can give a hint on how to resolve it I will be grateful.
> > > > > > > Attached is the full serial dump.
> > > > > > > Thank you,
> > > > > > > Jose Trujillo
> > > > > > >
> > > > > > > ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> > > > > > >
> > > > > > > coreboot mailing list: coreboot at coreboot.org
> > > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot
> > > > > >
> > > > > > --
> > > > > > Best regards,
> > > > > > Naresh G. Solanki
> > > > > >
> > > > > > -----------------------------------
> > > > > >
> > > > > > coreboot mailing list: coreboot at coreboot.org
> > > > > > https://mail.coreboot.org/mailman/listinfo/coreboot
> > > > >
> > > > > --
> > > > > coreboot mailing list: coreboot at coreboot.org
> > > > > https://mail.coreboot.org/mailman/listinfo/coreboot
> > > >
> > > > --
> > > > Best regards,
> > > > Naresh G. Solanki
> > >
> > > --
> > > coreboot mailing list: coreboot at coreboot.org
> > > https://mail.coreboot.org/mailman/listinfo/coreboot
>
> --
>
> Best regards,
> Naresh G. Solanki