[coreboot] Questions about using coreboot riscv with qemu

[Jonathan Neuschäfer]

On Mon, Sep 10, 2018 at 10:03:14AM -0400, Liam Naddell wrote:
> This is my first time using a mailing list btw, sorry.

Hi and welcome,

> 
> I was wondering how I could test the images I have built with `make
> riscv-crossgcc && make` using qemu.
> 
> 
> I tried running qemu-system-riscv64(the one gotten from the riscv-linux
> port), with the name of the image produced(coreboot.rom), and it did
> nothing.
> 
> qemu-system-riscv64 ./build/coreboot.rom
> 
> qemu-system-riscv64: Trying to execute code outside RAM or ROM at
> 0x0000000000000000

coreboot's support for qemu-system-riscv* is quite outdated, it would
probably need some work before it functions again.

Spike has seen more recent work, but SiFive's devboard (the HiFive
Unleashed) has seen the most recent work.

> I also tried this using the -bios flag, and by using the make-spike-elf
> script with the -bios flag, and I still got nothing.

Hmm, I'm not sure how QEMU is supposed to be invoked for RISC-V.



Jonathan Neuschäfer
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://mail.coreboot.org/pipermail/coreboot/attachments/20180910/e1980470/attachment.asc>