[coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

Rudolf Marek r.marek at assembler.cz
Mon Jun 25 20:39:19 CEST 2018


Dne 25.6.2018 v 09:01 Jonathan Neuschäfer napsal(a):
> If this is the Denali DDR controller, do you think it would be possible
> to simply read the initial configuration out of the registers of a
> booted system?  (In any case, that's probably worth trying.)

Perhaps it could work with the existing coreboot code. Basically it seems the PHY addresses are
just black boxes and the configuration is mostly black box. Plus some logic is needed. See rockchip/rk3399/sdram.c
Maybe some bits needs to be initially 0, and written later.

Another suspicious coincidence that it is denali is this:

         * work around controller bug:
         * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
        copy_to_reg(&denali_ctl[1], &params_ctl[1],
                    sizeof(struct rk3399_ddr_pctl_regs) - 4);
        write32(&denali_ctl[0], params_ctl[0]);

You see, it writes the first register last. As the DRAM_CLASS is defined to be first register in sifive
manual in bits 11:8. The LPDDR3 seems to be 6 in coreboot sources, and the sifive manual says DDR3 is 6 and DDR4 is 0xa
which matches and also bit position seems to match!

There is also some denali support in the u-boot it seems.

Plus this seems to be some old iteration:


Seems to document some of it.

Search terms: "denali"  "CASLAT_LIN"
or "denali" "dram_class"


More information about the coreboot mailing list