[coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board
citypw at gmail.com
Mon Jun 25 09:33:04 CEST 2018
On Mon, Jun 25, 2018 at 2:46 AM, Jonathan Neuschäfer
<j.neuschaefer at gmx.net> wrote:
> On Fri, Jun 22, 2018 at 01:01:04PM +0200, Jonathan Neuschäfer wrote:
>> Section 20.3 describes the initialization sequence for the DRAM
>> controller, but leaves out the values for the register for "memory
>> timing settings, PAD mode configuration, initialization, and training."
>> It says: "Please contact SiFive directly to determine the complete
>> register settings for your application."
>> I will ask on the forum.
> "While we’d love to provide you with this information, we believe we
> cannot. However, we can’t prevent anyone from disassembling the fsbl and
> copying the values sent to the blackbox DDR register map."
> (-- https://forums.sifive.com/t/ddr-controller-configuration-register-values-for-hifive-unleashed/1334/3)
Thanks, seems our only option is to reversing.
GNU powered it...
GPL protect it...
God blessing it...
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