[coreboot] Bayley Bay FSP-based CRB

Nico Huber nico.h at gmx.de
Thu Jun 21 10:27:10 CEST 2018

On 21.06.2018 02:34, Zvi Vered wrote:
> In case of PCIe enumeration, the generation of PCIe (1,2,3) can be set> Should vendor supply code for this ? or any other information ?

PCIe configuration is SoC specific and should be done by FSP. However,
I can't find any PCIe specific settings for the BayTrail FSP.

As this is one of the earlier FSP releases, it is not unlikely that
it does not expose all the option Intel's reference code provides. I'll
add the maintainers of the BayTrail FSP hook-up in CC. Maybe they can
tell us more about it.

> How can I write it from scratch ?  Can Intel provide information on how to
> implement this initialization ?

AFAIK, Intel does not document PCIe initialization and encourages every-
one to use their reference code (which is compiled into FSP). It's a
shame that they don't allow open-source implementations because we can't
make any alterations to FSP once Intel thinks it's finished (which is
almost always too early, IMHO).


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