[coreboot] Atom c3000 Harcuvar and Intel ME

[mark pleso]

My questions are:1. has anyone else seen a hang during smm relocation, w/cb 4.6/4.7, on a Broadwell-DE?2. if so, is the wbinvd() a valid way to resolve the hang?3. should our wbinvd() fix be upstreamed, without fully understanding why it is needed?
All of code (cb, fsp, microcode, etc.) worked just fine with CB 4.5.  With 4.6 and 4.7 LOGLEVEL=7 was needed to make things boot (by adding delays apparently).  
We configured CB with menuconfig and specified "Intel" as the platform.  We are using an Intel supplied FSP binary.  Kevin Herbert did the CB work, adding him to the thread.
Thank you,Mark 

    On Monday, February 26, 2018 2:49 PM, Philipp Stanner <stanner at posteo.de> wrote:
 

 Am Montag, den 26.02.2018, 17:14 -0300 schrieb Sumo:
> Hi,
> 
> In the coreboot build menu there is no option regarding the Intel ME
> integration.
> The 'coreboot.rom' file is the full SPI flash image or this file is
> suitable to
> replace the BIOS region of the SPI flash (0x00800000--0x00ffffff)?
> (i.e. in the SPI flash we already have a region for Intel ME
> firmware)

I'm not sure what the question is. 

When configuring CB with menuconfig you have to select your platform
and type in the path to your ME-binary-blob. The later has to be
provided by you; meaning you have to extract the BIOS from the flash,
extract the ME-binary using coreboot/utils, clean it with ME-cleaner
(optional) and then build coreboot with your blob.

The toolchain takes care automatically about the correct placement of
the ME in the right address-ranges.

I hope this was helpful.

> Thanks,
> Sumo

-- 
coreboot mailing list: coreboot at coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

   
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot/attachments/20180226/1727dc57/attachment.html>