<html><head></head><body><div style="color:#000; background-color:#fff; font-family:Courier New, courier, monaco, monospace, sans-serif;font-size:16px"><div id="yui_3_16_0_ym19_1_1519685333884_14304">My questions are:</div><div id="yui_3_16_0_ym19_1_1519685333884_14304" dir="ltr">1. has anyone else seen a hang during smm relocation, w/cb 4.6/4.7, on a Broadwell-DE?</div><div id="yui_3_16_0_ym19_1_1519685333884_14304">2. if so, is the wbinvd() a valid way to resolve the hang?</div><div id="yui_3_16_0_ym19_1_1519685333884_14304">3. should our wbinvd() fix be upstreamed, without fully understanding why it is needed?</div><div id="yui_3_16_0_ym19_1_1519685333884_14304"><br></div><div id="yui_3_16_0_ym19_1_1519685333884_14304">All of code (cb, fsp, microcode, etc.) worked just fine with CB 4.5. With 4.6 and 4.7 LOGLEVEL=7 was needed to make things boot (by adding delays apparently). </div><div id="yui_3_16_0_ym19_1_1519685333884_14304"><br></div><div id="yui_3_16_0_ym19_1_1519685333884_14304" dir="ltr">We configured CB with menuconfig and specified "Intel" as the platform. We are using an Intel supplied FSP binary. Kevin Herbert did the CB work, adding him to the thread.</div><div id="yui_3_16_0_ym19_1_1519685333884_14304" dir="ltr"><br></div><div id="yui_3_16_0_ym19_1_1519685333884_14304" dir="ltr">Thank you,</div><div id="yui_3_16_0_ym19_1_1519685333884_14304" dir="ltr">Mark</div> <div class="qtdSeparateBR"><br><br></div><div class="yahoo_quoted" style="display: block;"> <div style="font-family: Courier New, courier, monaco, monospace, sans-serif; font-size: 16px;"> <div style="font-family: HelveticaNeue, Helvetica Neue, Helvetica, Arial, Lucida Grande, sans-serif; font-size: 16px;"> <div dir="ltr"><font size="2" face="Arial"> On Monday, February 26, 2018 2:49 PM, Philipp Stanner <stanner@posteo.de> wrote:<br></font></div> <br><br> <div class="y_msg_container"><div dir="ltr">Am Montag, den 26.02.2018, 17:14 -0300 schrieb Sumo:<br></div><div dir="ltr">> Hi,<br></div><div dir="ltr">> <br></div><div dir="ltr">> In the coreboot build menu there is no option regarding the Intel ME<br></div><div dir="ltr">> integration.<br></div><div dir="ltr">> The 'coreboot.rom' file is the full SPI flash image or this file is<br></div><div dir="ltr">> suitable to<br></div><div dir="ltr">> replace the BIOS region of the SPI flash (0x00800000--0x00ffffff)?<br></div><div dir="ltr">> (i.e. in the SPI flash we already have a region for Intel ME<br></div><div dir="ltr">> firmware)<br></div><div dir="ltr"><br></div><div dir="ltr">I'm not sure what the question is. <br></div><div dir="ltr"><br></div><div dir="ltr">When configuring CB with menuconfig you have to select your platform<br></div><div dir="ltr">and type in the path to your ME-binary-blob. The later has to be<br></div><div dir="ltr">provided by you; meaning you have to extract the BIOS from the flash,<br></div><div dir="ltr">extract the ME-binary using coreboot/utils, clean it with ME-cleaner<br></div><div dir="ltr">(optional) and then build coreboot with your blob.<br></div><div dir="ltr"><br></div><div dir="ltr">The toolchain takes care automatically about the correct placement of<br></div><div dir="ltr">the ME in the right address-ranges.<br></div><div dir="ltr"><br></div><div dir="ltr">I hope this was helpful.<br></div><div dir="ltr"><br></div><div dir="ltr">> Thanks,<br></div><div dir="ltr">> Sumo<br></div><div dir="ltr"><br></div><div dir="ltr">-- <br></div><div dir="ltr">coreboot mailing list: <a ymailto="mailto:coreboot@coreboot.org" href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br></div><div dir="ltr"><a href="https://mail.coreboot.org/mailman/listinfo/coreboot" target="_blank">https://mail.coreboot.org/mailman/listinfo/coreboot</a></div><br><br></div> </div> </div> </div></div></body></html>