[coreboot] Looking for a volunteer to add Fam15h spectre MSR to coreboot

Arthur Heymans arthur at aheymans.xyz
Tue Apr 10 02:32:33 CEST 2018


Linux already does that for you: (v4.16) arch/x86/kernel/cpu/amd.c line 869.

Kind regards

On 5 April 2018 00:51:30 GMT+02:00, "Taiidan at gmx.com" <Taiidan at gmx.com> wrote:
>As I am not a programmer I do not know how to do this (thanks for the
>heads-up rmarek) nor am I permitted to add to the repos.
>MITIGATION G-2                                       
>Description: Set an MSR in the processor so that LFENCE is a dispatch
>serializing instruction and then
>use LFENCE in code streams to serialize dispatch (LFENCE is faster than
>RDTSCP which is also dispatch
>This mode of LFENCE may be enabled by setting MSR C001_1029[1]=1.
>This is important and covers a variety of boards such as the KGPE-D16,
>KCMA-D8 and G505s (all the last and best owner controlled x86_64

Arthur Heymans
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