[coreboot] Looking for a volunteer to add Fam15h spectre MSR to coreboot

Taiidan at gmx.com Taiidan at gmx.com
Thu Apr 5 00:51:30 CEST 2018

As I am not a programmer I do not know how to do this (thanks for the
heads-up rmarek) nor am I permitted to add to the repos.

MITIGATION G-2                                       
Description: Set an MSR in the processor so that LFENCE is a dispatch
serializing instruction and then
use LFENCE in code streams to serialize dispatch (LFENCE is faster than
RDTSCP which is also dispatch

This mode of LFENCE may be enabled by setting MSR C001_1029[1]=1.

This is important and covers a variety of boards such as the KGPE-D16,
KCMA-D8 and G505s (all the last and best owner controlled x86_64 systems)

-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0xDF372A17.asc
Type: application/pgp-keys
Size: 5247 bytes
Desc: not available
URL: <http://mail.coreboot.org/pipermail/coreboot/attachments/20180404/bc51067a/attachment.skr>

More information about the coreboot mailing list