[coreboot] Coreboot on X230 and Dualboot / How to make it work

[One7two99]

Hello Nico,

> I suspect some misconfiguration or that something confuses the libpay-
> load VGA driver (which these two secondary payload rely on).

This might be true, but I don't understand why I can see the SeaBios Menu (Press ESC) and can also use graphical boot (Windows and Qubes OS) but the secondary payloads don't work.
Can you check my .config especially the setting for the VGA device?

>> If you thing I"ve missed out important steps, I am happy to hear your comments.
> Don"t think you missed anything [...] But you might do too much already.
> Especially flashing anything but the BIOS region when you want to track
> down coreboot issues makes things harder to reason about.

I had the seconday payloads booting when lynxis did the coreboot flashing.
But we flashed without adding a vga-rom so that I couldn't boot into windows.
I've extracted the vga rom and then tried to rebuild coreboot, but I  seem to miss some configuration to get graphical boot (vga rom) and secondary payload boot running.

I've seen the following option in make nconfig for coreboot under "General Setup":
│    [*] Include the coreboot .config file into the ROM image                │

QUESTION:
How can I extract this .config file? I could then extract this from my first flashing together with lynxis to see which settings have been applied there.

> Please attach your .config file. Nobody can say anything for sure
> with-out knowing what you chose.

I've attached the config file and will also list the activated options here:
(only enabled options are shown):

[General Setup]
│    [*] Use CMOS for configuration values
│    [*] Compress ramstage with LZMA
│    [*] Include the coreboot .config file into the ROM image
│    [*] Create a table of timestamps collected during boot
│    -*- Build the ramstage to be relocatable in 32-bit address space

[Mainboard]
│    Mainboard vendor (Lenovo)
│       Mainboard model (ThinkPad X230)
│       ROM chip size (12288 KB (12 MB))
│       (0x400000) Size of CBFS filesystem in ROM

[Chipset]
│     *** CPU ***
│ [*] Enable VMX for virtualization
│ [*]   Set lock bit after configuring VMX
│     Include CPU microcode in CBFS (Generate from tree)
│     *** Northbridge ***
│ -*- Use native raminit
│     *** Southbridge ***
│     Flash locking during chipset lockdown (Don't lock flash sections)
│ [*] Lock down chipset in coreboot
│     *** Embedded Controllers ***
│ [*] Beep on fatal error
│ [*] Flash LEDs on fatal error
│    *** Intel Firmware ***
│ [*] Add Intel descriptor.bin file
│     (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin)
│ [*]   Add Intel ME/TXE firmware
│     (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin)
│ [*]     Verify the integrity of the supplied ME/TXE firmware
│ [*]   Add gigabit ethernet firmware
│     (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin)
│ [*] Lock ME/TXE section
│     Verified Boot (vboot)
│     Bootblock behaviour (Always load fallback)

[Devices]
│     Graphics initialization (Use native graphics init)
|       --> Framebuffer mode (Legacy VGA text mode)
│     Display
│ -*- Enable PCIe Common Clock                                               │
│ -*- Enable PCIe ASPM
[*] Add a VGA BIOS image
│     (./3rdparty/blobs/mainboard/lenovo/x230/pci8086,0166.rom) VGA BIOS
│     (8086,0166) VGA device PCI IDs

[Generic Drivers]
│           [*] Serial port on SuperIO
│           [*] Support Intel PCI-e WiFi adapters
│           [*] PS/2 keyboard init
│           [*] Enable TPM support

[Console]
│       [*] Squelch AP CPUs from early console.
│       [*] Send console output to a CBMEM buffer
│           (0x20000) Room allocated for console output in CBMEM
│       [*]   Send POST codes to an external device
│               Device to send POST codes to (None)
│       [*]   Send POST codes to an IO port
│           (0x80)  IO port for POST codes

[System tables]
│       [*] Generate SMBIOS tables

[Payload]
│     Add a payload (SeaBIOS)  --->                                          │
│     SeaBIOS version (1.10.2)  --->                                         │
│     (0) PS/2 keyboard controller initialization timeout (milliseconds)     │
│ [*] Hardware init during option ROM execution                              │
│     ()  SeaBIOS config file                                                │
│     ()  SeaBIOS bootorder file                                             │
│     (-1) SeaBIOS debug level (verbosity)                                   │
│       *** Using default SeaBIOS log level ***                              │
│ [*] Use LZMA compression for payloads                                      │
│     Secondary Payloads  --->
│               [*] Load coreinfo as a secondary payload
│               [*] Load nvramcui as a secondary payload

[Debugging]
all deactivated

kind regards

[788]
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