[coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?
matt.devillier at gmail.com
Sat Nov 4 17:01:17 CET 2017
On Sat, Nov 4, 2017 at 7:16 AM, Nico Huber <nico.h at gmx.de> wrote:
> Hi Matt, Jay,
> On 04.11.2017 03:25, Matt DeVillier wrote:
>> Hi Jay,
>> the SKL/KBL FSP blob published on Github is compatible with the headers
>> currently in coreboot, with the exception of the MEMORY_INFO_DATA_HOB - as
>> is, coreboot will not be able to parse the HOB and populate the SMBIOS
>> tables (minor adjustment needed, see: https://pastebin.com/Um9m7X43), but
>> otherwise it should boot and run without issue (at least it does on the
>> handful of SKL devices I've used it with, using both DDR3 and DDR4). The
>> FSP signatures absolutely should match, so I'm not sure why you're seeing
> I'm not sure what versions you are comparing, I see many more diffe-
> rences between Kabylake FSP from github (54b6a31) and upstream sky-
> kabylake in coreboot (b2b2015, see attachment). Also in UPD values
> (SpiFlashCfgLockDown and ThreeStrikeCounterDisable were added to FSPS
> UPD, the former is used in coreboot).
> Do I miss something? Is there another more recent published binary?
sorry my original msg was unclear - you are correct that the SKL/KBL FSP2
headers in coreboot do add a few new fields (though the majority of the
diff is comment changes). I only meant to convey that the Github binary
should boot with the coreboot headers, and is seemingly functional with the
exception of the SMBIOS HOB/table issue.
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the coreboot