<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Sat, Nov 4, 2017 at 7:16 AM, Nico Huber <span dir="ltr"><<a href="mailto:nico.h@gmx.de" target="_blank">nico.h@gmx.de</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Matt, Jay,<span class=""><br>
<br>
On 04.11.2017 03:25, Matt DeVillier wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi Jay,<br>
<br>
the SKL/KBL FSP blob published on Github is compatible with the headers<br>
currently in coreboot, with the exception of the MEMORY_INFO_DATA_HOB - as<br>
is, coreboot will not be able to parse the HOB and populate the SMBIOS<br>
tables (minor adjustment needed, see: <a href="https://pastebin.com/Um9m7X43" rel="noreferrer" target="_blank">https://pastebin.com/Um9m7X43</a>)<wbr>, but<br>
otherwise it should boot and run without issue (at least it does on the<br>
handful of SKL devices I've used it with, using both DDR3 and DDR4). The<br>
FSP signatures absolutely should match, so I'm not sure why you're seeing<br>
otherwise<br>
</blockquote>
<br></span>
I'm not sure what versions you are comparing, I see many more diffe-<br>
rences between Kabylake FSP from github (54b6a31) and upstream sky-<br>
kabylake in coreboot (b2b2015, see attachment). Also in UPD values<br>
(SpiFlashCfgLockDown and ThreeStrikeCounterDisable were added to FSPS<br>
UPD, the former is used in coreboot).<br>
<br>
Do I miss something? Is there another more recent published binary?<span class="HOEnZb"><font color="#888888"><br>
<br>
Nico</font></span></blockquote><div><br></div><div>sorry my original msg was unclear - you are correct that the SKL/KBL FSP2 headers in coreboot do add a few new fields (though the majority of the diff is comment changes). I only meant to convey that the Github binary should boot with the coreboot headers, and is seemingly functional with the exception of the SMBIOS HOB/table issue.</div></div></div></div>