[coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

[Nico Huber]

Hi Jay,

On 04.11.2017 01:26, Jay Talbott wrote:
> I'm trying to get coreboot up and running on an Intel RVP15 CRB, which is
> the same as the RVP7 except that the RVP15 has DDR4 memory instead of DDR3.
> 
> There is a mainboard solution for the RVP7 in coreboot. However, the current
> KabyLake FSP published on GitHub doesn't seem like it's the right FSP for
> the SkyLake-U/KabyLake-U. If nothing else, there's a problem with that FSP
> such that the signature in the FSP-M UPD header does not match the signature
> in the corresponding header files, so when the FSP 2.0 driver in coreboot
> goes to check that they are a match, execution dies right there.
> 
>       if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
>             die("Invalid FSPM signature!\n");
> 
> (coreboot/src/drivers/intel/fsp2_0/memory_init.c, in function
> do_fsp_memory_init)
> 
> I don't want to bypass that check in the code in case the FSP posted to
> GitHub isn't the right FSP for this particular SoC.

the FSP binary is probably the correct one, but you have to separate it
into three pieces: FSP-T, FSP-M, FSP-S. Did you do that? Only FSP-M and
FSP-S are needed in coreboot. There is a script (SplitFspBin.py in EDK
II) that can separate the blobs, I have no idea why Intel puts them to-
gether at all.

IIRC, there is no version check on the binary. You have to compare the
header files used in coreboot and those that come with the binary manu-
ally. Generally, the binaries on github work with corebot. But they seem
to come out of a different development process at Intel. The Intel deve-
lopers working on coreboot seem to have no clue that the binaries on
github exist at all. And if you compare the history of the header files
in coreboot to those on github you'll see that Intel either pushes the
wrong headers or the binaries on github and the binaries used for core-
boot development are not from the same branch. It's really creepy (and
hard to tell which of the versions are the one with the backdoors oO).

> Obviously, somebody at Intel has the right FSP that works for these boards
> in order to validate that the coreboot implementation worked prior to
> upstreaming it to the repo. I'm just not sure how to get the right one so
> that I can get this booting.

As you have access to a CRB, your contact to Intel is probably better
than mine. You have to ask Intel. OEMs/ODMs/IBVs, they all seem to have
access to the binaries used for coreboot development... IMHO, a huge
offense to the coreboot community that we get to maintain the code for
blobs that we'll never see; not even the binaries!

> Furthermore, I have yet to get the serial console working on the DB-9 serial
> port. I have the jumpers on the board configured to connect it to UART #2,
> and configured in coreboot accordingly, but I get nothing for console
> output.

Please attach your .config file and point to the source revision you are
using. Hard to tell anything w/o the code.

Nico