[coreboot] Problems changing payload on Intel Leaf Hill

[Tahnia Lichtenstein]

Hi Mario,

Thank you very much for sharing, that already helps a lot!! I can spot
quite a lot of differences to my own build settings.

I've been pursuing a Grub2 payload in the meantime (no success so far),
will now return to SeaBIOS and try and incorporate the necessary changes
you suggested.

Just a couple of questions so far:

   - Are you able to boot Yocto with the current combination you have?
   - I have all the blobs around coreboot, except the VBIOS... I have tried
   all the options in https://www.coreboot.org/VGA_support, but I suspect
   the reference bootloader images provided by Intel does not use a VBIOS
   file. I also cannot find a suitable VBIOS on Intel's website. (By the way,
   thanks for the FIT decomposition tip, I did not know this was possible... I
   took great pains to find the correct blobs on Intel's website, would have
   been much easier to just use FIT!) Where did you obtain a VBIOS file?
   - Is it specifically VBIOS, or is it a VBT.dat file? Or are you running
   SeaVGABIOS?

Many thanks again!

Best regards,
Tahnia

On Fri, Nov 3, 2017 at 2:01 PM, Scheithauer, Mario <
Mario.Scheithauer at siemens.com> wrote:

>
> Hi Cameron,
>
> > Did you modify the FSP blobs at all?
> Yes, we made some adjustments for our mainboard (mc_apl1).
> But they shouldn’t play a decisive role (power states, PCIe settings).
>
> > The reason I ask is that my coreboot build hangs in the FspSiliconInit().
> Then you will get pretty far.
> We are currently still using the MR2 FSP package for APL-I.
> As IFWI template we use the BIOS version v178.10 for the CRBs.
> These components are provided by Intel.
> That’s it. The CRB should boot with this combination.
>
> Mario
>
> > -----Ursprüngliche Nachricht-----
> > Von: Cameron Craig [mailto:Cameron.Craig at exterity.com]
> > Gesendet: Freitag, 3. November 2017 11:51
> > An: Scheithauer, Mario (DF MC MTS R&D SWRT 4); ahW at n
> > Cc: coreboot at coreboot.org
> > Betreff: Re: [coreboot] Problems changing payload on Intel Leaf Hill
> >
> > Hi Mario,
> >
> > I've been attempting to build coreboot(master) for the Leaf Hill CRB,
> with no
> > success so far.
> >
> > Did you modify the FSP blobs at all?
> > I had a look at your config, the filenames "FSP_MR2_M_ECC_MOD" caught my
> > eye.
> >
> > The reason I ask is that my coreboot build hangs in the FspSiliconInit().
> >
> > Cheers,
> > Cameron
> >
> >
> >
> > Cameron Craig | Graduate Software Engineer | Exterity Limited
> > tel: +44 1383 828 250 | fax:  | mobile:
> > e: Cameron.Craig at exterity.com | w: www.exterity.com
> >
> >
> >
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