[coreboot] Problems changing payload on Intel Leaf Hill

Scheithauer, Mario Mario.Scheithauer at siemens.com
Fri Nov 3 11:18:34 CET 2017

Hi Ahwan,

Oh sorry, I forgot to attach the .config file for coreboot in my previous mail.
We have adjusted the memory settings (romstage.c) in the leafhill directory for the Oxbow Hill CRB. With these settings the memory initialization should work for Juniper Hill and Oxbow Hill CRB. Both CRBs use the same memory modules – DDR3L. But for the Leaf Hill CRB you need different settings, because there are other DIMM modules on it – LPDDR4.


Von: coreboot [mailto:coreboot-bounces at coreboot.org] Im Auftrag von ahW at n via coreboot
Gesendet: Freitag, 3. November 2017 08:38
An: coreboot at coreboot.org
Betreff: Re: [coreboot] Problems changing payload on Intel Leaf Hill

Hi Mario,

I read your reply and saw you have APL CRB Oxbow Hill with coreboot + SeaBios running.
I am using the same board and wanted to build the coreboot but failed.
I think I have the required files ready (bootable UEFI BIOS file, fitimage.bin, Fsp.fd ...)
But still failed to build my coreboot.
I wonder I am having correct .config settings.
Can you share your settings?
I check the attachment in previous list but all that is for leafhill, I wonder are they same and valid for both Oxbox Hill and Leafhill?
Please advise, thank you.

- ahwan

> Scheithauer, Mario Mario.Scheithauer at siemens.com<http://siemens.com>
> Wed Nov 1 16:28:45 CET 2017
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> Hi Tahnia,
> We have an APL CRB Oxbow Hill (B0-stepping) with coreboot (master) + SeaBios (master) running.
> Attached are all necessary coreboot adaptions and the config file for SeaBios.
> After the generation, a hack in coreboot.rom is still necessary so that SeaBios can find the VBIOS.
> SeaBios expects at the end of the CBFS the address from the beginning of the CBFS section (see SeaBiosPointer.jpg).
> Furthermore you have to pay attention to the IGD PCI ID. Intel uses different PCI Device IDs in different CPU versions for IGD (5a84 or 5a85).
> The console output only works via MMIO on the CRB. Therefore you need the LPSS UART0 Micro USB port.
> With all these adjustments we can boot a system on the CRB and have full console output.
> Now you just need all the necessary blobs around coreboot (IFWI, FSP, VBIOS, uCode).
> You can use the Intel FIT tool to separate the most of the components from the original BIOS.
> Hope that helps,
> Mario
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