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<p class="MsoNormal"><span lang="EN-US" style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">Hi Ahwan,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">Oh sorry, I forgot to attach the .config file for coreboot in my previous mail.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">We have adjusted the memory settings (romstage.c) in the leafhill directory for the Oxbow Hill CRB. With these settings the memory initialization
should work for Juniper Hill and Oxbow Hill CRB. Both CRBs use the same memory modules – DDR3L. But for the Leaf Hill CRB you need different settings, because there are other DIMM modules on it – LPDDR4.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D">Mario<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">Von:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> coreboot [mailto:coreboot-bounces@coreboot.org]
<b>Im Auftrag von </b>ahW@n via coreboot<br>
<b>Gesendet:</b> Freitag, 3. November 2017 08:38<br>
<b>An:</b> coreboot@coreboot.org<br>
<b>Betreff:</b> Re: [coreboot] Problems changing payload on Intel Leaf Hill<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">Hi Mario,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">I read your reply and saw you have APL CRB Oxbow Hill with coreboot + SeaBios running.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">I am using the same board and wanted to build the coreboot but failed.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">I think I have the required files ready (bootable UEFI BIOS file, fitimage.bin, Fsp.fd ...)<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">But still failed to build my coreboot.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">I wonder I am having correct .config settings.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">Can you share your settings?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">I check the attachment in previous list but all that is for leafhill, I wonder are they same and valid for both Oxbox Hill and Leafhill?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">Please advise, thank you.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif"">- ahwan<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Verdana","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Scheithauer, Mario Mario.Scheithauer at
<a href="http://siemens.com">siemens.com</a> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Wed Nov 1 16:28:45 CET 2017</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Previous message (by thread): [coreboot] Coreboot support on H8SGL-F</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Next message (by thread): [coreboot] Problems changing payload on Intel Leaf Hill</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Hi Tahnia,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> We have an APL CRB Oxbow Hill (B0-stepping) with coreboot (master) + SeaBios (master) running.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Attached are all necessary coreboot adaptions and the config file for SeaBios.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> After the generation, a hack in coreboot.rom is still necessary so that SeaBios can find the VBIOS.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> SeaBios expects at the end of the CBFS the address from the beginning of the CBFS section (see SeaBiosPointer.jpg).</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Furthermore you have to pay attention to the IGD PCI ID. Intel uses different PCI Device IDs in different CPU versions for IGD (5a84 or 5a85).</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> The console output only works via MMIO on the CRB. Therefore you need the LPSS UART0 Micro USB port.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> With all these adjustments we can boot a system on the CRB and have full console output.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Now you just need all the necessary blobs around coreboot (IFWI, FSP, VBIOS, uCode).</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> You can use the Intel FIT tool to separate the most of the components from the original BIOS.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Hope that helps,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">> Mario</span><o:p></o:p></p>
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