[coreboot] More details about ram issues

Nico Huber nico.h at gmx.de
Tue Nov 15 23:14:36 CET 2016

On 14.11.2016 20:40, Charlotte Plusplus wrote:
> Ooops, my mistake. You are right, I did not understand the difference
> between IO voltage and VDD voltage.
> I should have been more careful, I was wrong, sorry :-(
> In case anyone is interested in making the hardware support 1.35V (which I
> won't do), here is the specsheet for the voltage regulator. It has equation
> 6 explaining how to chose R2 to get the wanted voltage.
> http://www.ti.com/lit/ds/symlink/tps51916.pdf
> Supporting 1.35V should just be a matter of swapping R2, which can still be
> hard with SMD. Maybe when the motherboards are cheap enough?

I'm not sure if supply voltage is the only thing to change for DDR3L.

Anyway, depending on the package of that resistor it might be the easi-
est to solder another one on top (to lower the overall resistance).


> On Sat, Nov 12, 2016 at 6:46 PM, Nico Huber <nico.h at gmx.de> wrote:
>> On 12.11.2016 05:00, Charlotte Plusplus wrote:
>>> Hello
>>> On Fri, Nov 11, 2016 at 5:37 PM, Nico Huber <nico.h at gmx.de> wrote:
>>>>> The W520 does only have 1.5V DDR voltage. If it's stable with vendor
>>>>> bios, it's not a DDR voltage problem at all.
>>> Based on my reading of the block diagram and crossing that with a cpu
>>> pinout and the cpu specs, I disagree.  The W520 indeed only support 1.5V,
>>> if you mean 1.5V vs 1.3 "low voltage" DDR3L.
>>> But SA_DIMM_VREFDQ is in direct control of the DDR3 voltage: "The step
>> size
>>> is 7.7 mV". So it supports 1.5V +- k*0.007V, with k being given by the
>> XMP
>>> profile.
>>> In case this is not clear, on
>>> http://www.intel.com/content/dam/www/public/us/en/
>> documents/datasheets/3rd-gen-core-family-mobile-vol-1-datasheet.pdf
>>> :
>>> Page 30 : "The processor memory controller has the capability of
>> generating
>>> the DDR3 Reference  Voltage (VREF) internally for both read (RDVREF) and
>>> write (VREFDQ) operations. The generated VREF can be changed in small
>>> steps, and an optimum VREF value is  determined for both during a cold
>> boot
>>> through advanced DDR3 training procedures in  order to provide the best
>>> voltage and signal margins."
>>> That seems to be a lot of evidence in the voltage not being an absolutely
>>> fixed 1.500V. It is something more flexible!!!
>> You're confusing the memory's operating voltage (what XMP and DDR3 vs.
>> DDR3L is about) with i/o voltages. VrefCA is the reference for Command/
>> Address lines and VrefDQ is the reference for Data lines from what I
>> understand.
>> For the operating voltage have a look at page 86 in the Kendo-3 schema-
>> tics. The TPS51916 provides the voltage VCC1R5A which is VDD for the
>> DIMMs. You can see from its datasheet that it's controlled by REFIN
>> which is generated by dividing VTTREF (1.8V) by the resistors R1056
>> (10K) and R843 (48K7). If those resistors were configurable in any
>> way, you could control the operating voltage. But they are just plain
>> resistors.
>> So even if the processor had dedicated pins to control the voltage, they
>> are not used in this machine.
>> Nico

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