[coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
scott at notabs.org
Tue Jun 7 18:29:31 CEST 2011
Kevin O'Connor wrote:
]I agree that no one would notice 7ms on it's own. However, a handful
]of 7ms improvements can be noticed.
]I think of the bootblock as the place to fully map the flash device.
]So, why would it be out of place to enable the faster flash accesses
]in the bootblock?
The reason the patch code seems out of place is that the original code
enables the flash enhancements early (before memory initialization)
in sb800/sbpor.c. The patch moves this sb800 setting even earlier. That
is good, except that the sb800 setting is no longer grouped together
with other sb800 code. Instead, it is in romstage.c, which doesn't
usually embed chipset code. A better solution might be to move the flash
enhancement enabling code to an earlier position within sbpor.c. While
sbpor.c executes very early, it runs a fair amount of code before
enabling prefetch and SPI 33 MHz.
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