[coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
marcj303 at gmail.com
Tue Jun 7 19:26:13 CEST 2011
On Tue, Jun 7, 2011 at 10:29 AM, Scott Duplichan <scott at notabs.org> wrote:
> Kevin O'Connor wrote:
> ]I agree that no one would notice 7ms on it's own. However, a handful
> ]of 7ms improvements can be noticed.
> ]I think of the bootblock as the place to fully map the flash device.
> ]So, why would it be out of place to enable the faster flash accesses
> ]in the bootblock?
> Hello Kevin,
> The reason the patch code seems out of place is that the original code
> enables the flash enhancements early (before memory initialization)
> in sb800/sbpor.c. The patch moves this sb800 setting even earlier. That
> is good, except that the sb800 setting is no longer grouped together
> with other sb800 code. Instead, it is in romstage.c, which doesn't
> usually embed chipset code. A better solution might be to move the flash
> enhancement enabling code to an earlier position within sbpor.c. While
> sbpor.c executes very early, it runs a fair amount of code before
> enabling prefetch and SPI 33 MHz.
There are southbridge specific bootblock.c functions which enable
access etc., so moving the prefetch settings should be fine.
Can SPI be programmed to 33MHz always? Does it depend on the device or
platform? It may need to be a configuration option or a romstage.c
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