[coreboot] [commit] r6627 - trunk/src/mainboard/asrock/e350m1
kevin at koconnor.net
Tue Jun 7 02:14:28 CEST 2011
On Sun, Jun 05, 2011 at 02:39:22AM -0500, Scott Duplichan wrote:
> Stefan Reinauer wrote:
> ]Also, enabling Prefetch and 33MHz fast read mode should possibly go in the
> ]southbridge's bootblock.c so the first cbfs scan does not run with the
> ]slow settings.
> Together the changes save 7 ms. The question is, where do we draw the line
> on boot time reduction? I worked in a group a while back where a manager
> said, "every millisecond counts". This was due to a desire to make a
> customer's board boot more quickly than a board from a competitor. Certainly
> no user can notice a boot time difference of a few ms. The difference is
> easy to measure though, and in some cases a few ms is enough to affect who
> calls their board fastest. On the other hand, coreboot+seabios is already
> several thousand ms faster than UEFI, so maybe saving 7 ms is not worth the
> somewhat out of place code.
I agree that no one would notice 7ms on it's own. However, a handful
of 7ms improvements can be noticed.
I think of the bootblock as the place to fully map the flash device.
So, why would it be out of place to enable the faster flash accesses
in the bootblock?
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