[coreboot] DL145G3

[samuel]

>>We need to figure out where pin 8 on the flash chip is connected. It
>>is the TBL# pin, which implements hardware write protect for the top
>>64KB of the chip. Hopefully it connects to a chip which we can find
>>documentation for easily. Then the code is easy to add.
Will check and report back. Machine is sitting at home...

>>Do you have access to a continuity tester? Please check this
>>connection.
I do not have access to a continuity tester.

>> * You can insulate the #TBL pin of the flash chip from the
>>   corresponding socket contact, and connect #TBL to Vdd. According
>>   to the datasheet of SST49LF080A, providing Vih(=Vdd) to #TBL
>>   disables write protection on the boot block.
I guess i can try this... I suppose it won't hurt?

>>Correct. It is most likely the cause. But - it would also be
>>interesting if you could measure the voltage Samuel, on pin 8
>>after having run flashrom in any mode.
I will get a volt meter... What pin should i use as ground? I tried
having a look at page 7 of the LPC data sheet but i didn't see a
ground pin...