[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl1: Activate clock center spreading depth for PTN3460

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28761


Change subject: siemens/mc_apl1: Activate clock center spreading depth for PTN3460
......................................................................

siemens/mc_apl1: Activate clock center spreading depth for PTN3460

In order to minimize Electromagnetic Interference (EMI) from PTN3460
bridge device, clock frequency center spreading depth must be activated
for mc_apl1 mainboard. The clock spreading depth is set to 1 % of the
modulation frequency.

Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/28761/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
index f1cbf0f..ed03cf3 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
@@ -84,8 +84,8 @@
 		/* Use 18 bits per pixel. */
 		cfg.lvds_interface_ctrl1 |= 0x20;
 
-	/* No clock spreading, 300 mV LVDS swing. */
-	cfg.lvds_interface_ctrl2 = 0x03;
+	/* 1 % clock center spreading, 300 mV LVDS swing. */
+	cfg.lvds_interface_ctrl2 = 0x13;
 	/* No LVDS signal swap. */
 	cfg.lvds_interface_ctrl3 = 0x00;
 	/* Delay T2 (VDD to LVDS active) by 16 ms. */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9
Gerrit-Change-Number: 28761
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
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