[coreboot-gerrit] Change in coreboot[master]: ec/google/chromeec: set SCI event mask early on s0

[dhaval v sharma (Code Review)]

dhaval v sharma has uploaded this change for review. ( https://review.coreboot.org/28721


Change subject: ec/google/chromeec: set SCI event mask early on s0
......................................................................

ec/google/chromeec: set SCI event mask early on s0

Change helps in avoiding an ACPI switch SMI later

Change-Id: Ib4d2b3e12d1d63dba29c5365c5a2fbf7b221226b
Signed-off-by: Dhaval <dhaval.v.sharma at intel.com>
---
M src/ec/google/chromeec/ec.c
1 file changed, 7 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/28721/1

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 90fcc3d..17ee13a 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -474,9 +474,6 @@
 		while (google_chromeec_get_event() != 0)
 			;
 
-		/* Restore SCI event mask. */
-		google_chromeec_set_sci_mask(info->sci_events);
-
 	} else {
 		google_chromeec_set_smi_mask(info->smi_events);
 
@@ -489,6 +486,13 @@
 					info->s3_wake_events,
 					info->s0ix_wake_events);
 	}
+	/* Should be okay to set sci mask for s0 path also because
+	 * anyways SCI interrupt gets enabled later during PMC init
+	 * stage this way we can avoid additional ACPI switch SMI
+	 * later */
+
+	google_chromeec_set_sci_mask(info->sci_events);
+
 
 	/* Clear wake event mask. */
 	google_chromeec_set_wake_mask(0);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib4d2b3e12d1d63dba29c5365c5a2fbf7b221226b
Gerrit-Change-Number: 28721
Gerrit-PatchSet: 1
Gerrit-Owner: dhaval v sharma <dhaval.v.sharma at intel.com>
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