[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add new cannon lake PCH-H support

[PraveenX Hodagatta Pranesh (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/28718

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Add new cannon lake PCH-H support
......................................................................

soc/intel/cannonlake: Add new cannon lake PCH-H support

Cannon lake PCH-H is added to support coffeelake RVP11 and coffeelake
RVP8 platforms.

- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
  SRAM, AUDIO, CSE0, XDCI, SD, Northbridge and Graphics device.

- Add new device IDs to intel common code respectively.

- Add CPU,LPC,GD,MCH entry to report_platform.c to identify RVP11 & RVP8.

- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
  is modified accordingly.

- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.

BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
     are enumerated and cross checked devices ids in serial logs and UEFI shell.

Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh at intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/include/soc/pci_devs.h
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
19 files changed, 148 insertions(+), 14 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28718/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Gerrit-Change-Number: 28718
Gerrit-PatchSet: 2
Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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