[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add new cannon lake PCH-H support
PraveenX Hodagatta Pranesh (Code Review)
gerrit at coreboot.org
Mon Sep 24 08:33:56 CEST 2018
PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/28718
Change subject: soc/intel/cannonlake: Add new cannon lake PCH-H support
......................................................................
soc/intel/cannonlake: Add new cannon lake PCH-H support
Cannon lake PCH-H is added to support coffeelake RVP11 and coffeelake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, Northbridge and Graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU,LPC,GD,MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh at intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/include/soc/pci_devs.h
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
19 files changed, 136 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28718/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a6ed6d9..e40d663 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2689,6 +2689,8 @@
#define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85
#define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84
#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83
+#define PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370 0xa306
+#define PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370 0xa30c
/* Intel PCIE device ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
@@ -2767,6 +2769,31 @@
#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6
#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP1 0xa338
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP2 0xa339
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP3 0xa33a
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP4 0xa33b
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP5 0xa33c
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP6 0xa33d
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP7 0xa33e
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP8 0xa33f
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP9 0xa330
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP10 0xa331
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP11 0xa332
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP12 0xa333
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP13 0xa334
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP14 0xa335
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP15 0xa336
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP16 0xa337
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP17 0xa340
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP18 0xa341
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP19 0xa342
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP20 0xa343
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP21 0xa32c
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP22 0xa32d
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP23 0xa32e
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP24 0xa32f
+
/* Intel SATA device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03
#define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07
@@ -2786,6 +2813,7 @@
#define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94
#define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194
#define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1
+#define PCI_DEVICE_ID_INTEL_CNL_H_PMC 0xa321
/* Intel I2C device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60
@@ -2820,6 +2848,10 @@
#define PCI_DEVICE_ID_INTEL_CNL_I2C3 0x9deb
#define PCI_DEVICE_ID_INTEL_CNL_I2C4 0x9dc5
#define PCI_DEVICE_ID_INTEL_CNL_I2C5 0x9dc6
+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C0 0xa368
+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C1 0xa369
+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C2 0xa36a
+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C3 0xa36b
/* Intel UART device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27
@@ -2842,6 +2874,9 @@
#define PCI_DEVICE_ID_INTEL_CNL_UART0 0x9da8
#define PCI_DEVICE_ID_INTEL_CNL_UART1 0x9da9
#define PCI_DEVICE_ID_INTEL_CNL_UART2 0x9dc7
+#define PCI_DEVICE_ID_INTEL_CNL_H_UART0 0xa328
+#define PCI_DEVICE_ID_INTEL_CNL_H_UART1 0xa329
+#define PCI_DEVICE_ID_INTEL_CNL_H_UART2 0xa347
/* Intel SPI device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24
@@ -2887,6 +2922,8 @@
#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42
#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A
#define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5
+#define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b
+#define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
@@ -2907,12 +2944,15 @@
#define PCI_DEVICE_ID_INTEL_WHL_ID_Wx4 0x3E34
#define PCI_DEVICE_ID_INTEL_WHL_ID_Wx2 0x3E35
#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0
+#define PCI_DEVICE_ID_INTEL_CNL_ID_H 0x3ec4
+#define PCI_DEVICE_ID_INTEL_CNL_ID_S 0x3ec2
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
#define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123
#define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS 0xa1a3
#define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3
+#define PCI_DEVICE_ID_INTEL_CNL_H_SMBUS 0xa323
/* Intel XHCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
@@ -2921,16 +2961,19 @@
#define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f
#define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa2af
#define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded
+#define PCI_DEVICE_ID_INTEL_CNL_H_XHCI 0xa36d
/* Intel P2SB device Ids */
#define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92
#define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192
#define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0
+#define PCI_DEVICE_ID_INTEL_CNL_H_P2SB 0xa320
/* Intel SRAM device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec
#define PCI_DEVICE_ID_INTEL_GLK_SRAM 0x31ec
#define PCI_DEVICE_ID_INTEL_CNL_SRAM 0x9def
+#define PCI_DEVICE_ID_INTEL_CNL_H_SRAM 0xa36f
/* Intel AUDIO device Ids */
#define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98
@@ -2938,24 +2981,28 @@
#define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8
#define PCI_DEVICE_ID_INTEL_SKL_AUDIO 0x9d70
#define PCI_DEVICE_ID_INTEL_KBL_AUDIO 0x9d71
+#define PCI_DEVICE_ID_INTEL_CNL_H_AUDIO 0xa348
/* Intel HECI/ME device Ids */
#define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a
#define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a
#define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0
#define PCI_DEVICE_ID_INTEL_SKL_CSE0 0x9d3a
+#define PCI_DEVICE_ID_INTEL_CNL_H_CSE0 0xa360
/* Intel XDCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa
#define PCI_DEVICE_ID_INTEL_GLK_XDCI 0x31aa
#define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI 0x9d30
#define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI 0x9dee
+#define PCI_DEVICE_ID_INTEL_CNL_H_XDCI 0xa36e
/* Intel SD device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
#define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d
#define PCI_DEVICE_ID_INTEL_CNL_SD 0x9df5
+#define PCI_DEVICE_ID_INTEL_CNL_H_SD 0xa375
/* Intel EMMC device Ids */
#define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b
@@ -2968,6 +3015,8 @@
#define PCH_CNL_LP_U_PREMIUM 0x9d84
#define PCH_CNL_LP_U_BASE 0x9d85
#define PCH_CNL_H_DT_SUPER 0xa280
+#define PCH_CNL_H_MOBILE_Q370 0xa306
+#define PCH_CNL_H_MOBILE_QM370 0xa30c
/* Intel WIFI Ids */
#define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 256cf1b..7bfda6b 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -82,8 +82,9 @@
select CONSOLE_SERIAL
select BOOTBLOCK_CONSOLE
select DRIVERS_UART
- select DRIVERS_UART_8250MEM_32
- select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32 if !CANNONLAKE_SOC_PCH_H
+ select NO_UART_ON_SUPERIO if !CANNONLAKE_SOC_PCH_H
+ select DRIVERS_UART_8250IO if CANNONLAKE_SOC_PCH_H
config UART_FOR_CONSOLE
int "Index for LPSS UART port to use for console"
@@ -204,6 +205,7 @@
config SOC_INTEL_I2C_DEV_MAX
int
+ default 4 if CANNONLAKE_SOC_PCH_H
default 6
# Clock divider parameters for 115200 baud rate
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 937e56c..26ca375 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -38,6 +38,7 @@
{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
{ CPUID_COFFEELAKE_D0, "Coffeelake D0" },
{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},
+ { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" },
};
static struct {
@@ -49,6 +50,8 @@
{ PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"},
{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)"},
{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)"},
+ { PCI_DEVICE_ID_INTEL_CNL_ID_H, "Coffelake-H" },
+ { PCI_DEVICE_ID_INTEL_CNL_ID_S, "CoffeeLake-S" },
};
static struct {
@@ -58,6 +61,8 @@
{ PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
{ PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
{ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
+ { PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370, "Cannonlake-H Q370" },
+ { PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370, "Cannonlake-H QM370" },
};
static struct {
@@ -74,6 +79,8 @@
{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
{ PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"},
{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"},
+ { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake H GT2" },
+ { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake S GT2" },
};
static uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 30719ed..8c555c7 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -74,6 +74,14 @@
case PCH_DEVFN_PCIE14: return "RP14";
case PCH_DEVFN_PCIE15: return "RP15";
case PCH_DEVFN_PCIE16: return "RP16";
+ case PCH_DEVFN_PCIE17: return "RP17";
+ case PCH_DEVFN_PCIE18: return "RP18";
+ case PCH_DEVFN_PCIE19: return "RP19";
+ case PCH_DEVFN_PCIE20: return "RP20";
+ case PCH_DEVFN_PCIE21: return "RP21";
+ case PCH_DEVFN_PCIE22: return "RP22";
+ case PCH_DEVFN_PCIE23: return "RP23";
+ case PCH_DEVFN_PCIE24: return "RP24";
case PCH_DEVFN_UART0: return "UAR0";
case PCH_DEVFN_UART1: return "UAR1";
case PCH_DEVFN_GSPI0: return "SPI0";
@@ -109,8 +117,10 @@
PCH_DEVFN_I2C1,
PCH_DEVFN_I2C2,
PCH_DEVFN_I2C3,
+#if !IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)
PCH_DEVFN_I2C4,
PCH_DEVFN_I2C5,
+#endif
PCH_DEVFN_GSPI0,
PCH_DEVFN_GSPI1,
PCH_DEVFN_GSPI2,
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 4d677de..b574d4d 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -147,6 +147,24 @@
#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6)
#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)
+#define PCH_DEV_SLOT_PCIE_2 0x1b
+#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0)
+#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1)
+#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2)
+#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3)
+#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4)
+#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5)
+#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6)
+#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7)
+#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0)
+#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1)
+#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2)
+#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3)
+#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4)
+#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5)
+#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6)
+#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7)
+
#define PCH_DEV_SLOT_SIO3 0x1e
#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0)
#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1)
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index ae1ba4d..4b75a6c 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -157,7 +157,10 @@
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
m_cfg->SaGv = config->SaGv;
- m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+ if (IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H))
+ m_cfg->UserBd = BOARD_TYPE_DESKTOP;
+ else
+ m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
m_cfg->RMT = config->RMT;
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 4b53117..44e7417 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -518,6 +518,7 @@
PCI_DEVICE_ID_INTEL_GLK_CSE0,
PCI_DEVICE_ID_INTEL_CNL_CSE0,
PCI_DEVICE_ID_INTEL_SKL_CSE0,
+ PCI_DEVICE_ID_INTEL_CNL_H_CSE0,
0,
};
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index 365fab7..2b11cd8 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -31,6 +31,7 @@
PCI_DEVICE_ID_INTEL_CNL_AUDIO,
PCI_DEVICE_ID_INTEL_GLK_AUDIO,
PCI_DEVICE_ID_INTEL_SKL_AUDIO,
+ PCI_DEVICE_ID_INTEL_CNL_H_AUDIO,
0,
};
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 74a5cae..14eef9b 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -133,6 +133,8 @@
PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,
PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,
PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
+ PCI_DEVICE_ID_INTEL_CFL_H_GT2,
+ PCI_DEVICE_ID_INTEL_CFL_S_GT2,
0,
};
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index 11bd018..34b076f 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -190,6 +190,10 @@
PCI_DEVICE_ID_INTEL_GLK_I2C5,
PCI_DEVICE_ID_INTEL_GLK_I2C6,
PCI_DEVICE_ID_INTEL_GLK_I2C7,
+ PCI_DEVICE_ID_INTEL_CNL_H_I2C0,
+ PCI_DEVICE_ID_INTEL_CNL_H_I2C1,
+ PCI_DEVICE_ID_INTEL_CNL_H_I2C2,
+ PCI_DEVICE_ID_INTEL_CNL_H_I2C3,
0,
};
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index ef8417a..c34a85c 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -145,6 +145,8 @@
PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,
PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,
PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
+ PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370,
+ PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370,
0
};
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index c09c6aa..5f3c910 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -166,6 +166,7 @@
PCI_DEVICE_ID_INTEL_APL_P2SB,
PCI_DEVICE_ID_INTEL_GLK_P2SB,
PCI_DEVICE_ID_INTEL_CNL_P2SB,
+ PCI_DEVICE_ID_INTEL_CNL_H_P2SB,
0,
};
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index c4b266a..15ae132 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -166,6 +166,30 @@
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14,
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15,
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP1,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP2,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP3,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP4,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP5,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP6,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP7,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP8,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP9,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP10,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP11,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP12,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP13,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP14,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP15,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP16,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP17,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP18,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP19,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP20,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP21,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP22,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP23,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP24,
0
};
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index c8e8026..e1faf9c 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -127,6 +127,7 @@
PCI_DEVICE_ID_INTEL_KBP_H_PMC,
PCI_DEVICE_ID_INTEL_APL_PMC,
PCI_DEVICE_ID_INTEL_GLK_PMC,
+ PCI_DEVICE_ID_INTEL_CNL_H_PMC,
0
};
diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c
index 811d273..9f56ee6 100644
--- a/src/soc/intel/common/block/scs/sd.c
+++ b/src/soc/intel/common/block/scs/sd.c
@@ -69,6 +69,7 @@
PCI_DEVICE_ID_INTEL_CNL_SD,
PCI_DEVICE_ID_INTEL_GLK_SD,
PCI_DEVICE_ID_INTEL_SKL_SD,
+ PCI_DEVICE_ID_INTEL_CNL_H_SD,
0
};
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 45ee940..41a5f47 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -305,6 +305,8 @@
PCI_DEVICE_ID_INTEL_KBL_U_R,
PCI_DEVICE_ID_INTEL_KBL_ID_DT,
PCI_DEVICE_ID_INTEL_CFL_ID_U,
+ PCI_DEVICE_ID_INTEL_CNL_ID_H,
+ PCI_DEVICE_ID_INTEL_CNL_ID_S,
0
};
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 12b99e7..4632c4e 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -263,6 +263,9 @@
PCI_DEVICE_ID_INTEL_GLK_UART1,
PCI_DEVICE_ID_INTEL_GLK_UART2,
PCI_DEVICE_ID_INTEL_GLK_UART3,
+ PCI_DEVICE_ID_INTEL_CNL_H_UART0,
+ PCI_DEVICE_ID_INTEL_CNL_H_UART1,
+ PCI_DEVICE_ID_INTEL_CNL_H_UART2,
0,
};
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index eb330ee..b7a6398 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -42,6 +42,7 @@
PCI_DEVICE_ID_INTEL_CNL_LP_XDCI,
PCI_DEVICE_ID_INTEL_GLK_XDCI,
PCI_DEVICE_ID_INTEL_SPT_LP_XDCI,
+ PCI_DEVICE_ID_INTEL_CNL_H_XDCI,
0
};
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index c38d19f..6e3535b 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -43,6 +43,7 @@
PCI_DEVICE_ID_INTEL_SPT_LP_XHCI,
PCI_DEVICE_ID_INTEL_SPT_H_XHCI,
PCI_DEVICE_ID_INTEL_KBP_H_XHCI,
+ PCI_DEVICE_ID_INTEL_CNL_H_XHCI,
0
};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Gerrit-Change-Number: 28718
Gerrit-PatchSet: 1
Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
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