<p>PraveenX Hodagatta Pranesh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28718">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add new cannon lake PCH-H support<br><br>Cannon lake PCH-H is added to support coffeelake RVP11 and coffeelake<br>RVP8 platforms.<br><br>- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,<br> SRAM, AUDIO, CSE0, XDCI, SD, Northbridge and Graphics device.<br><br>- Add new device IDs to intel common code respectively.<br><br>- Add CPU,LPC,GD,MCH entry to report_platform.c to identify RVP11 & RVP8.<br><br>- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c<br> is modified accordingly.<br><br>- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.<br><br>BUG=None<br>TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices<br> are enumerated and cross checked devices ids in serial logs and UEFI shell.<br><br>Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4<br>Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com><br>---<br>M src/include/device/pci_ids.h<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/bootblock/report_platform.c<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/include/soc/pci_devs.h<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>M src/soc/intel/common/block/cse/cse.c<br>M src/soc/intel/common/block/dsp/dsp.c<br>M src/soc/intel/common/block/graphics/graphics.c<br>M src/soc/intel/common/block/i2c/i2c.c<br>M src/soc/intel/common/block/lpc/lpc.c<br>M src/soc/intel/common/block/p2sb/p2sb.c<br>M src/soc/intel/common/block/pcie/pcie.c<br>M src/soc/intel/common/block/pmc/pmc.c<br>M src/soc/intel/common/block/scs/sd.c<br>M src/soc/intel/common/block/systemagent/systemagent.c<br>M src/soc/intel/common/block/uart/uart.c<br>M src/soc/intel/common/block/xdci/xdci.c<br>M src/soc/intel/common/block/xhci/xhci.c<br>19 files changed, 136 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28718/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h</span><br><span>index a6ed6d9..e40d663 100644</span><br><span>--- a/src/include/device/pci_ids.h</span><br><span>+++ b/src/include/device/pci_ids.h</span><br><span>@@ -2689,6 +2689,8 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370 0xa306</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370 0xa30c</span><br><span> </span><br><span> /* Intel PCIE device ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10</span><br><span>@@ -2767,6 +2769,31 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP1 0xa338</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP2 0xa339</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP3 0xa33a</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP4 0xa33b</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP5 0xa33c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP6 0xa33d</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP7 0xa33e</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP8 0xa33f</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP9 0xa330</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP10 0xa331</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP11 0xa332</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP12 0xa333</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP13 0xa334</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP14 0xa335</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP15 0xa336</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP16 0xa337</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP17 0xa340</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP18 0xa341</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP19 0xa342</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP20 0xa343</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP21 0xa32c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP22 0xa32d</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP23 0xa32e</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP24 0xa32f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Intel SATA device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07</span><br><span>@@ -2786,6 +2813,7 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94</span><br><span> #define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_PMC 0xa321</span><br><span> </span><br><span> /* Intel I2C device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60</span><br><span>@@ -2820,6 +2848,10 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_I2C3 0x9deb</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_I2C4 0x9dc5</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_I2C5 0x9dc6</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C0 0xa368</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C1 0xa369</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C2 0xa36a</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C3 0xa36b</span><br><span> </span><br><span> /* Intel UART device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27</span><br><span>@@ -2842,6 +2874,9 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_UART0 0x9da8</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_UART1 0x9da9</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_UART2 0x9dc7</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_UART0 0xa328</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_UART1 0xa329</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_UART2 0xa347</span><br><span> </span><br><span> /* Intel SPI device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24</span><br><span>@@ -2887,6 +2922,8 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A</span><br><span> #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92</span><br><span> </span><br><span> /* Intel Northbridge Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0</span><br><span>@@ -2907,12 +2944,15 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_WHL_ID_Wx4 0x3E34</span><br><span> #define PCI_DEVICE_ID_INTEL_WHL_ID_Wx2 0x3E35</span><br><span> #define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_ID_H 0x3ec4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_ID_S 0x3ec2</span><br><span> </span><br><span> /* Intel SMBUS device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123</span><br><span> #define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS 0xa1a3</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_SMBUS 0xa323</span><br><span> </span><br><span> /* Intel XHCI device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8</span><br><span>@@ -2921,16 +2961,19 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f</span><br><span> #define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa2af</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_XHCI 0xa36d</span><br><span> </span><br><span> /* Intel P2SB device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92</span><br><span> #define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_P2SB 0xa320</span><br><span> </span><br><span> /* Intel SRAM device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec</span><br><span> #define PCI_DEVICE_ID_INTEL_GLK_SRAM 0x31ec</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_SRAM 0x9def</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_SRAM 0xa36f</span><br><span> </span><br><span> /* Intel AUDIO device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98</span><br><span>@@ -2938,24 +2981,28 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8</span><br><span> #define PCI_DEVICE_ID_INTEL_SKL_AUDIO 0x9d70</span><br><span> #define PCI_DEVICE_ID_INTEL_KBL_AUDIO 0x9d71</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_AUDIO 0xa348</span><br><span> </span><br><span> /* Intel HECI/ME device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a</span><br><span> #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0</span><br><span> #define PCI_DEVICE_ID_INTEL_SKL_CSE0 0x9d3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_CSE0 0xa360</span><br><span> </span><br><span> /* Intel XDCI device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa</span><br><span> #define PCI_DEVICE_ID_INTEL_GLK_XDCI 0x31aa</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI 0x9d30</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI 0x9dee</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_XDCI 0xa36e</span><br><span> </span><br><span> /* Intel SD device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca</span><br><span> #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca</span><br><span> #define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_SD 0x9df5</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_SD 0xa375</span><br><span> </span><br><span> /* Intel EMMC device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b</span><br><span>@@ -2968,6 +3015,8 @@</span><br><span> #define PCH_CNL_LP_U_PREMIUM 0x9d84</span><br><span> #define PCH_CNL_LP_U_BASE 0x9d85</span><br><span> #define PCH_CNL_H_DT_SUPER 0xa280</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_CNL_H_MOBILE_Q370 0xa306</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_CNL_H_MOBILE_QM370 0xa30c</span><br><span> </span><br><span> /* Intel WIFI Ids */</span><br><span> #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084</span><br><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 256cf1b..7bfda6b 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -82,8 +82,9 @@</span><br><span> select CONSOLE_SERIAL</span><br><span> select BOOTBLOCK_CONSOLE</span><br><span> select DRIVERS_UART</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_UART_8250MEM_32</span><br><span style="color: hsl(0, 100%, 40%);">- select NO_UART_ON_SUPERIO</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_UART_8250MEM_32 if !CANNONLAKE_SOC_PCH_H</span><br><span style="color: hsl(120, 100%, 40%);">+ select NO_UART_ON_SUPERIO if !CANNONLAKE_SOC_PCH_H</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_UART_8250IO if CANNONLAKE_SOC_PCH_H</span><br><span> </span><br><span> config UART_FOR_CONSOLE</span><br><span> int "Index for LPSS UART port to use for console"</span><br><span>@@ -204,6 +205,7 @@</span><br><span> </span><br><span> config SOC_INTEL_I2C_DEV_MAX</span><br><span> int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4 if CANNONLAKE_SOC_PCH_H</span><br><span> default 6</span><br><span> </span><br><span> # Clock divider parameters for 115200 baud rate</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>index 937e56c..26ca375 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>@@ -38,6 +38,7 @@</span><br><span> { CPUID_CANNONLAKE_D0, "Cannonlake D0" },</span><br><span> { CPUID_COFFEELAKE_D0, "Coffeelake D0" },</span><br><span> { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},</span><br><span style="color: hsl(120, 100%, 40%);">+ { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" },</span><br><span> };</span><br><span> </span><br><span> static struct {</span><br><span>@@ -49,6 +50,8 @@</span><br><span> { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"},</span><br><span> { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)"},</span><br><span> { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)"},</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_ID_H, "Coffelake-H" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_ID_S, "CoffeeLake-S" },</span><br><span> };</span><br><span> </span><br><span> static struct {</span><br><span>@@ -58,6 +61,8 @@</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370, "Cannonlake-H Q370" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370, "Cannonlake-H QM370" },</span><br><span> };</span><br><span> </span><br><span> static struct {</span><br><span>@@ -74,6 +79,8 @@</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },</span><br><span> { PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"},</span><br><span> { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"},</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake H GT2" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake S GT2" },</span><br><span> };</span><br><span> </span><br><span> static uint8_t get_dev_revision(pci_devfn_t dev)</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 30719ed..8c555c7 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -74,6 +74,14 @@</span><br><span> case PCH_DEVFN_PCIE14: return "RP14";</span><br><span> case PCH_DEVFN_PCIE15: return "RP15";</span><br><span> case PCH_DEVFN_PCIE16: return "RP16";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE17: return "RP17";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE18: return "RP18";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE19: return "RP19";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE20: return "RP20";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE21: return "RP21";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE22: return "RP22";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE23: return "RP23";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE24: return "RP24";</span><br><span> case PCH_DEVFN_UART0: return "UAR0";</span><br><span> case PCH_DEVFN_UART1: return "UAR1";</span><br><span> case PCH_DEVFN_GSPI0: return "SPI0";</span><br><span>@@ -109,8 +117,10 @@</span><br><span> PCH_DEVFN_I2C1,</span><br><span> PCH_DEVFN_I2C2,</span><br><span> PCH_DEVFN_I2C3,</span><br><span style="color: hsl(120, 100%, 40%);">+#if !IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span> PCH_DEVFN_I2C4,</span><br><span> PCH_DEVFN_I2C5,</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> PCH_DEVFN_GSPI0,</span><br><span> PCH_DEVFN_GSPI1,</span><br><span> PCH_DEVFN_GSPI2,</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h</span><br><span>index 4d677de..b574d4d 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h</span><br><span>@@ -147,6 +147,24 @@</span><br><span> #define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6)</span><br><span> #define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_SLOT_PCIE_2 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define PCH_DEV_SLOT_SIO3 0x1e</span><br><span> #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0)</span><br><span> #define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1)</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>index ae1ba4d..4b75a6c 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>@@ -157,7 +157,10 @@</span><br><span> m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;</span><br><span> m_cfg->IedSize = CONFIG_IED_REGION_SIZE;</span><br><span> m_cfg->SaGv = config->SaGv;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->UserBd = BOARD_TYPE_ULT_ULX;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H))</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->UserBd = BOARD_TYPE_DESKTOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->UserBd = BOARD_TYPE_ULT_ULX;</span><br><span> m_cfg->RMT = config->RMT;</span><br><span> </span><br><span> for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {</span><br><span>diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c</span><br><span>index 4b53117..44e7417 100644</span><br><span>--- a/src/soc/intel/common/block/cse/cse.c</span><br><span>+++ b/src/soc/intel/common/block/cse/cse.c</span><br><span>@@ -518,6 +518,7 @@</span><br><span> PCI_DEVICE_ID_INTEL_GLK_CSE0,</span><br><span> PCI_DEVICE_ID_INTEL_CNL_CSE0,</span><br><span> PCI_DEVICE_ID_INTEL_SKL_CSE0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_CSE0,</span><br><span> 0,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c</span><br><span>index 365fab7..2b11cd8 100644</span><br><span>--- a/src/soc/intel/common/block/dsp/dsp.c</span><br><span>+++ b/src/soc/intel/common/block/dsp/dsp.c</span><br><span>@@ -31,6 +31,7 @@</span><br><span> PCI_DEVICE_ID_INTEL_CNL_AUDIO,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_AUDIO,</span><br><span> PCI_DEVICE_ID_INTEL_SKL_AUDIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_AUDIO,</span><br><span> 0,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c</span><br><span>index 74a5cae..14eef9b 100644</span><br><span>--- a/src/soc/intel/common/block/graphics/graphics.c</span><br><span>+++ b/src/soc/intel/common/block/graphics/graphics.c</span><br><span>@@ -133,6 +133,8 @@</span><br><span> PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,</span><br><span> PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,</span><br><span> PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CFL_H_GT2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CFL_S_GT2,</span><br><span> 0,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c</span><br><span>index 11bd018..34b076f 100644</span><br><span>--- a/src/soc/intel/common/block/i2c/i2c.c</span><br><span>+++ b/src/soc/intel/common/block/i2c/i2c.c</span><br><span>@@ -190,6 +190,10 @@</span><br><span> PCI_DEVICE_ID_INTEL_GLK_I2C5,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_I2C6,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_I2C7,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_I2C0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_I2C1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_I2C2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_I2C3,</span><br><span> 0,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c</span><br><span>index ef8417a..c34a85c 100644</span><br><span>--- a/src/soc/intel/common/block/lpc/lpc.c</span><br><span>+++ b/src/soc/intel/common/block/lpc/lpc.c</span><br><span>@@ -145,6 +145,8 @@</span><br><span> PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,</span><br><span> PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,</span><br><span> PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370,</span><br><span> 0</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c</span><br><span>index c09c6aa..5f3c910 100644</span><br><span>--- a/src/soc/intel/common/block/p2sb/p2sb.c</span><br><span>+++ b/src/soc/intel/common/block/p2sb/p2sb.c</span><br><span>@@ -166,6 +166,7 @@</span><br><span> PCI_DEVICE_ID_INTEL_APL_P2SB,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_P2SB,</span><br><span> PCI_DEVICE_ID_INTEL_CNL_P2SB,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_P2SB,</span><br><span> 0,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c</span><br><span>index c4b266a..15ae132 100644</span><br><span>--- a/src/soc/intel/common/block/pcie/pcie.c</span><br><span>+++ b/src/soc/intel/common/block/pcie/pcie.c</span><br><span>@@ -166,6 +166,30 @@</span><br><span> PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14,</span><br><span> PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15,</span><br><span> PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP3,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP4,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP5,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP6,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP7,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP8,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP9,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP10,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP11,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP12,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP13,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP14,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP15,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP16,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP17,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP18,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP19,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP20,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP21,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP22,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP23,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP24,</span><br><span> 0</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c</span><br><span>index c8e8026..e1faf9c 100644</span><br><span>--- a/src/soc/intel/common/block/pmc/pmc.c</span><br><span>+++ b/src/soc/intel/common/block/pmc/pmc.c</span><br><span>@@ -127,6 +127,7 @@</span><br><span> PCI_DEVICE_ID_INTEL_KBP_H_PMC,</span><br><span> PCI_DEVICE_ID_INTEL_APL_PMC,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_PMC,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_PMC,</span><br><span> 0</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c</span><br><span>index 811d273..9f56ee6 100644</span><br><span>--- a/src/soc/intel/common/block/scs/sd.c</span><br><span>+++ b/src/soc/intel/common/block/scs/sd.c</span><br><span>@@ -69,6 +69,7 @@</span><br><span> PCI_DEVICE_ID_INTEL_CNL_SD,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_SD,</span><br><span> PCI_DEVICE_ID_INTEL_SKL_SD,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_SD,</span><br><span> 0</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c</span><br><span>index 45ee940..41a5f47 100644</span><br><span>--- a/src/soc/intel/common/block/systemagent/systemagent.c</span><br><span>+++ b/src/soc/intel/common/block/systemagent/systemagent.c</span><br><span>@@ -305,6 +305,8 @@</span><br><span> PCI_DEVICE_ID_INTEL_KBL_U_R,</span><br><span> PCI_DEVICE_ID_INTEL_KBL_ID_DT,</span><br><span> PCI_DEVICE_ID_INTEL_CFL_ID_U,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_ID_H,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_ID_S,</span><br><span> 0</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c</span><br><span>index 12b99e7..4632c4e 100644</span><br><span>--- a/src/soc/intel/common/block/uart/uart.c</span><br><span>+++ b/src/soc/intel/common/block/uart/uart.c</span><br><span>@@ -263,6 +263,9 @@</span><br><span> PCI_DEVICE_ID_INTEL_GLK_UART1,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_UART2,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_UART3,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_UART0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_UART1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_UART2,</span><br><span> 0,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c</span><br><span>index eb330ee..b7a6398 100644</span><br><span>--- a/src/soc/intel/common/block/xdci/xdci.c</span><br><span>+++ b/src/soc/intel/common/block/xdci/xdci.c</span><br><span>@@ -42,6 +42,7 @@</span><br><span> PCI_DEVICE_ID_INTEL_CNL_LP_XDCI,</span><br><span> PCI_DEVICE_ID_INTEL_GLK_XDCI,</span><br><span> PCI_DEVICE_ID_INTEL_SPT_LP_XDCI,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_XDCI,</span><br><span> 0</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c</span><br><span>index c38d19f..6e3535b 100644</span><br><span>--- a/src/soc/intel/common/block/xhci/xhci.c</span><br><span>+++ b/src/soc/intel/common/block/xhci/xhci.c</span><br><span>@@ -43,6 +43,7 @@</span><br><span> PCI_DEVICE_ID_INTEL_SPT_LP_XHCI,</span><br><span> PCI_DEVICE_ID_INTEL_SPT_H_XHCI,</span><br><span> PCI_DEVICE_ID_INTEL_KBP_H_XHCI,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CNL_H_XHCI,</span><br><span> 0</span><br><span> };</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28718">change 28718</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28718"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4 </div>
<div style="display:none"> Gerrit-Change-Number: 28718 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> </div>