[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Move the FSP related callbacks to separate files
Rizwan Qureshi (Code Review)
gerrit at coreboot.org
Tue Sep 18 19:36:22 CEST 2018
Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28661
Change subject: soc/intel/cannonlake: Move the FSP related callbacks to separate files
......................................................................
soc/intel/cannonlake: Move the FSP related callbacks to separate files
Move funtions callbacks used to override FSP upd values to
separate files. This helps in compiling SoC code without referencing
the UPD structure params and hence not relying on the FSP header files
being released by Intel. The code will compile with basic header files
which only include the architectural FSP structures.
Add a Kconfig which allows plugging in these separate files for compilation.
The fact is, FSP header files are not released externally until PRQ.
However the teams at intel and some partners have access to the development
version of these files. To continue development on the pre-PRQ silicons and
submit related code to coreboot.org, this Kconfig helps in working with UPD
param overrides internally while still being to compile the code on
coreboot.org without the UPD structure definition.
BUG=None
BRANCH=None
TEST=Build for cnlrvp
Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip.c
A src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/romstage.h
M src/soc/intel/cannonlake/romstage/Makefile.inc
A src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/cannonlake/romstage/romstage.c
8 files changed, 285 insertions(+), 225 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/28661/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 256cf1b..5a74b6f 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -75,6 +75,7 @@
select UDELAY_TSC
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
+ select FSP_PARAM_OVERRIDE
config UART_DEBUG
bool "Enable UART debug port."
@@ -257,4 +258,11 @@
endchoice
+config FSP_PARAM_OVERRIDE
+ bool
+ default n
+ help
+ Use This should be selected if the SoC and the mainboard implement
+ function callbacks to populate/override the FSP UPD parameters.
+
endif
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 065d92b..761fe81 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -37,6 +37,7 @@
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += finalize.c
+ramstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += gspi.c
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 30719ed..0c0a05d 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -95,43 +95,6 @@
}
#endif
-static void parse_devicetree(FSP_S_CONFIG *params)
-{
- struct device *dev = SA_DEV_ROOT;
- if (!dev) {
- printk(BIOS_ERR, "Could not find root device\n");
- return;
- }
-
- const config_t *config = dev->chip_info;
- const int SerialIoDev[] = {
- PCH_DEVFN_I2C0,
- PCH_DEVFN_I2C1,
- PCH_DEVFN_I2C2,
- PCH_DEVFN_I2C3,
- PCH_DEVFN_I2C4,
- PCH_DEVFN_I2C5,
- PCH_DEVFN_GSPI0,
- PCH_DEVFN_GSPI1,
- PCH_DEVFN_GSPI2,
- PCH_DEVFN_UART0,
- PCH_DEVFN_UART1,
- PCH_DEVFN_UART2
- };
-
- for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) {
- dev = dev_find_slot(0, SerialIoDev[i]);
- if (!dev->enabled) {
- params->SerialIoDevMode[i] = PchSerialIoDisabled;
- continue;
- }
- params->SerialIoDevMode[i] = PchSerialIoPci;
- if (config->SerialIoDevMode[i] == PchSerialIoAcpi ||
- config->SerialIoDevMode[i] == PchSerialIoHidden)
- params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
- }
-}
-
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
@@ -177,139 +140,3 @@
.enable_dev = &soc_enable,
.init = &soc_init_pre_device,
};
-
-/* UPD parameters to be initialized before SiliconInit */
-void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
-{
- int i;
- FSP_S_CONFIG *params = &supd->FspsConfig;
- FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
- struct device *dev = SA_DEV_ROOT;
- config_t *config = dev->chip_info;
-
- /* Parse device tree and enable/disable devices */
- parse_devicetree(params);
-
- /* Load VBT before devicetree-specific config. */
- params->GraphicsConfigPtr = (uintptr_t)vbt_get();
-
- /* Set USB OC pin to 0 first */
- for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
- params->Usb2OverCurrentPin[i] = 0;
- }
-
- for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
- params->Usb3OverCurrentPin[i] = 0;
- }
-
- mainboard_silicon_init_params(params);
-
- /* Unlock upper 8 bytes of RTC RAM */
- params->PchLockDownRtcMemoryLock = 0;
-
- /* SATA */
- params->SataEnable = config->SataEnable;
- params->SataMode = config->SataMode;
- params->SataSalpSupport = config->SataSalpSupport;
- memcpy(params->SataPortsEnable, config->SataPortsEnable,
- sizeof(params->SataPortsEnable));
- memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
- sizeof(params->SataPortsDevSlp));
-
- /* Lan */
- params->PchLanEnable = config->PchLanEnable;
-
- /* Audio */
- params->PchHdaDspEnable = config->PchHdaDspEnable;
- params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
- params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
- params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
- params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
- params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
- params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
- params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
- params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
- params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
- params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
-
- /* S0ix */
- params->PchPmSlpS0Enable = config->s0ix_enable;
-
- /* USB */
- for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
- params->PortUsb20Enable[i] =
- config->usb2_ports[i].enable;
- params->Usb2OverCurrentPin[i] =
- config->usb2_ports[i].ocpin;
- params->Usb2AfePetxiset[i] =
- config->usb2_ports[i].pre_emp_bias;
- params->Usb2AfeTxiset[i] =
- config->usb2_ports[i].tx_bias;
- params->Usb2AfePredeemp[i] =
- config->usb2_ports[i].tx_emp_enable;
- params->Usb2AfePehalfbit[i] =
- config->usb2_ports[i].pre_emp_bit;
- }
-
- for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
- params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
- params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
- if (config->usb3_ports[i].tx_de_emp) {
- params->Usb3HsioTxDeEmphEnable[i] = 1;
- params->Usb3HsioTxDeEmph[i] =
- config->usb3_ports[i].tx_de_emp;
- }
- if (config->usb3_ports[i].tx_downscale_amp) {
- params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
- params->Usb3HsioTxDownscaleAmp[i] =
- config->usb3_ports[i].tx_downscale_amp;
- }
- }
-
- /* Enable xDCI controller if enabled in devicetree and allowed */
- dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
- if (!xdci_can_enable())
- dev->enabled = 0;
- params->XdciEnable = dev->enabled;
-
- /* PCI Express */
- for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
- if (config->PcieClkSrcUsage[i] == 0)
- config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
- }
- memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
- sizeof(config->PcieClkSrcUsage));
- memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
- sizeof(config->PcieClkSrcClkReq));
-
- /* eMMC and SD */
- params->ScsEmmcEnabled = config->ScsEmmcEnabled;
- params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
- params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
- if (config->EmmcHs400DllNeed == 1) {
- params->PchScsEmmcHs400RxStrobeDll1 =
- config->EmmcHs400RxStrobeDll1;
- params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;
- }
- params->ScsSdCardEnabled = config->ScsSdCardEnabled;
- params->ScsUfsEnabled = config->ScsUfsEnabled;
-
- params->Heci3Enabled = config->Heci3Enabled;
- params->Device4Enable = config->Device4Enable;
- params->SkipMpInit = !chip_get_fsp_mp_init();
-
- /* VrConfig Settings for 5 domains
- * 0 = System Agent, 1 = IA Core, 2 = Ring,
- * 3 = GT unsliced, 4 = GT sliced */
- for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
- fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
-
- /* Vt-D config */
- tconfig->VtdDisable = config->VtdDisable;
-}
-
-/* Mainboard GPIO Configuration */
-__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
new file mode 100644
index 0000000..4b983d6
--- /dev/null
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <compiler.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <intelblocks/xdci.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <string.h>
+
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+ struct device *dev = SA_DEV_ROOT;
+ if (!dev) {
+ printk(BIOS_ERR, "Could not find root device\n");
+ return;
+ }
+
+ const config_t *config = dev->chip_info;
+ const int SerialIoDev[] = {
+ PCH_DEVFN_I2C0,
+ PCH_DEVFN_I2C1,
+ PCH_DEVFN_I2C2,
+ PCH_DEVFN_I2C3,
+ PCH_DEVFN_I2C4,
+ PCH_DEVFN_I2C5,
+ PCH_DEVFN_GSPI0,
+ PCH_DEVFN_GSPI1,
+ PCH_DEVFN_GSPI2,
+ PCH_DEVFN_UART0,
+ PCH_DEVFN_UART1,
+ PCH_DEVFN_UART2
+ };
+
+ for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) {
+ dev = dev_find_slot(0, SerialIoDev[i]);
+ if (!dev->enabled) {
+ params->SerialIoDevMode[i] = PchSerialIoDisabled;
+ continue;
+ }
+ params->SerialIoDevMode[i] = PchSerialIoPci;
+ if (config->SerialIoDevMode[i] == PchSerialIoAcpi ||
+ config->SerialIoDevMode[i] == PchSerialIoHidden)
+ params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
+ }
+}
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+ int i;
+ FSP_S_CONFIG *params = &supd->FspsConfig;
+ FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
+ struct device *dev = SA_DEV_ROOT;
+ config_t *config = dev->chip_info;
+
+ /* Parse device tree and enable/disable devices */
+ parse_devicetree(params);
+
+ /* Load VBT before devicetree-specific config. */
+ params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+
+ /* Set USB OC pin to 0 first */
+ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
+ params->Usb2OverCurrentPin[i] = 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
+ params->Usb3OverCurrentPin[i] = 0;
+ }
+
+ mainboard_silicon_init_params(params);
+
+ /* Unlock upper 8 bytes of RTC RAM */
+ params->PchLockDownRtcMemoryLock = 0;
+
+ /* SATA */
+ params->SataEnable = config->SataEnable;
+ params->SataMode = config->SataMode;
+ params->SataSalpSupport = config->SataSalpSupport;
+ memcpy(params->SataPortsEnable, config->SataPortsEnable,
+ sizeof(params->SataPortsEnable));
+ memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
+ sizeof(params->SataPortsDevSlp));
+
+ /* Lan */
+ params->PchLanEnable = config->PchLanEnable;
+
+ /* Audio */
+ params->PchHdaDspEnable = config->PchHdaDspEnable;
+ params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
+ params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
+ params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
+ params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
+ params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
+ params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
+ params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
+ params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
+ params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
+ params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
+
+ /* S0ix */
+ params->PchPmSlpS0Enable = config->s0ix_enable;
+
+ /* USB */
+ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+ params->PortUsb20Enable[i] =
+ config->usb2_ports[i].enable;
+ params->Usb2OverCurrentPin[i] =
+ config->usb2_ports[i].ocpin;
+ params->Usb2AfePetxiset[i] =
+ config->usb2_ports[i].pre_emp_bias;
+ params->Usb2AfeTxiset[i] =
+ config->usb2_ports[i].tx_bias;
+ params->Usb2AfePredeemp[i] =
+ config->usb2_ports[i].tx_emp_enable;
+ params->Usb2AfePehalfbit[i] =
+ config->usb2_ports[i].pre_emp_bit;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+ params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].tx_de_emp) {
+ params->Usb3HsioTxDeEmphEnable[i] = 1;
+ params->Usb3HsioTxDeEmph[i] =
+ config->usb3_ports[i].tx_de_emp;
+ }
+ if (config->usb3_ports[i].tx_downscale_amp) {
+ params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+ params->Usb3HsioTxDownscaleAmp[i] =
+ config->usb3_ports[i].tx_downscale_amp;
+ }
+ }
+
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+
+ /* PCI Express */
+ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
+ if (config->PcieClkSrcUsage[i] == 0)
+ config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
+ }
+ memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
+ sizeof(config->PcieClkSrcUsage));
+ memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+ sizeof(config->PcieClkSrcClkReq));
+
+ /* eMMC and SD */
+ params->ScsEmmcEnabled = config->ScsEmmcEnabled;
+ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+ params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
+ if (config->EmmcHs400DllNeed == 1) {
+ params->PchScsEmmcHs400RxStrobeDll1 =
+ config->EmmcHs400RxStrobeDll1;
+ params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;
+ }
+ params->ScsSdCardEnabled = config->ScsSdCardEnabled;
+ params->ScsUfsEnabled = config->ScsUfsEnabled;
+
+ params->Heci3Enabled = config->Heci3Enabled;
+ params->Device4Enable = config->Device4Enable;
+ params->SkipMpInit = !chip_get_fsp_mp_init();
+
+ /* VrConfig Settings for 5 domains
+ * 0 = System Agent, 1 = IA Core, 2 = Ring,
+ * 3 = GT unsliced, 4 = GT sliced */
+ for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
+ fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
+
+ /* Vt-D config */
+ tconfig->VtdDisable = config->VtdDisable;
+}
+
+/* Mainboard GPIO Configuration */
+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h
index 9ea60ae..6faf110 100644
--- a/src/soc/intel/cannonlake/include/soc/romstage.h
+++ b/src/soc/intel/cannonlake/include/soc/romstage.h
@@ -18,6 +18,7 @@
#define _SOC_ROMSTAGE_H_
#include <arch/cpu.h>
+#include <chip.h>
#include <fsp/api.h>
void mainboard_memory_init_params(FSPM_UPD *mupd);
diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc
index 99bc25f..ab3e8e2 100644
--- a/src/soc/intel/cannonlake/romstage/Makefile.inc
+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc
@@ -15,4 +15,5 @@
romstage-y += power_state.c
romstage-y += romstage.c
+romstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
new file mode 100644
index 0000000..67aa0ec
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <chip.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
+{
+ unsigned int i;
+ uint32_t mask = 0;
+
+ /* Set IGD stolen size to 64MB. */
+ m_cfg->IgdDvmt50PreAlloc = 2;
+ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+ m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+ m_cfg->SaGv = config->SaGv;
+ m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+ m_cfg->RMT = config->RMT;
+
+ for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+ if (config->PcieRpEnable[i])
+ mask |= (1 << i);
+ }
+ m_cfg->PcieRpEnableMask = mask;
+ m_cfg->PrmrrSize = config->PrmrrSize;
+ m_cfg->EnableC6Dram = config->enable_c6dram;
+ /* Disable Cpu Ratio Override temporary. */
+ m_cfg->CpuRatio = 0;
+ m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+ /* Disable Vmx if Vt-d is already disabled */
+ if (config->VtdDisable)
+ m_cfg->VmxEnable = 0;
+ else
+ m_cfg->VmxEnable = config->VmxEnable;
+}
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ assert(dev != NULL);
+ const config_t *config = dev->chip_info;
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+ soc_memory_init_params(m_cfg, config);
+
+ /* Enable SMBus controller based on config */
+ m_cfg->SmbusEnable = config->SmbusEnable;
+ /* Set debug probe type */
+ m_cfg->PlatformDebugConsent = config->DebugConsent;
+
+ mainboard_memory_init_params(mupd);
+}
+
+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ /* Do nothing */
+}
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index ae1ba4d..113798d 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -146,55 +146,3 @@
run_postcar_phase(&pcf);
}
-
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
-{
- unsigned int i;
- uint32_t mask = 0;
-
- /* Set IGD stolen size to 64MB. */
- m_cfg->IgdDvmt50PreAlloc = 2;
- m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
- m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
- m_cfg->SaGv = config->SaGv;
- m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
- m_cfg->RMT = config->RMT;
-
- for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
- if (config->PcieRpEnable[i])
- mask |= (1 << i);
- }
- m_cfg->PcieRpEnableMask = mask;
- m_cfg->PrmrrSize = config->PrmrrSize;
- m_cfg->EnableC6Dram = config->enable_c6dram;
- /* Disable Cpu Ratio Override temporary. */
- m_cfg->CpuRatio = 0;
- m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
- /* Disable Vmx if Vt-d is already disabled */
- if (config->VtdDisable)
- m_cfg->VmxEnable = 0;
- else
- m_cfg->VmxEnable = config->VmxEnable;
-}
-
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
- assert(dev != NULL);
- const config_t *config = dev->chip_info;
- FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-
- soc_memory_init_params(m_cfg, config);
-
- /* Enable SMBus controller based on config */
- m_cfg->SmbusEnable = config->SmbusEnable;
- /* Set debug probe type */
- m_cfg->PlatformDebugConsent = config->DebugConsent;
-
- mainboard_memory_init_params(mupd);
-}
-
-__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
- /* Do nothing */
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e
Gerrit-Change-Number: 28661
Gerrit-PatchSet: 1
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
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