<p>Rizwan Qureshi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28661">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Move the FSP related callbacks to separate files<br><br>Move funtions callbacks used to override FSP upd values to<br>separate files. This helps in compiling SoC code without referencing<br>the UPD structure params and hence not relying on the FSP header files<br>being released by Intel. The code will compile with basic header files<br>which only include the architectural FSP structures.<br><br>Add a Kconfig which allows plugging in these separate files for compilation.<br>The fact is, FSP header files are not released externally until PRQ.<br>However the teams at intel and some partners have access to the development<br>version of these files. To continue development on the pre-PRQ silicons and<br>submit related code to coreboot.org, this Kconfig helps in working with UPD<br>param overrides internally while still being to compile the code on<br>coreboot.org without the UPD structure definition.<br><br>BUG=None<br>BRANCH=None<br>TEST=Build for cnlrvp<br><br>Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip.c<br>A src/soc/intel/cannonlake/fsp_params.c<br>M src/soc/intel/cannonlake/include/soc/romstage.h<br>M src/soc/intel/cannonlake/romstage/Makefile.inc<br>A src/soc/intel/cannonlake/romstage/fsp_params.c<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>8 files changed, 285 insertions(+), 225 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/28661/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 256cf1b..5a74b6f 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -75,6 +75,7 @@</span><br><span> select UDELAY_TSC</span><br><span> select UDK_2017_BINDING</span><br><span> select DISPLAY_FSP_VERSION_INFO</span><br><span style="color: hsl(120, 100%, 40%);">+ select FSP_PARAM_OVERRIDE</span><br><span> </span><br><span> config UART_DEBUG</span><br><span> bool "Enable UART debug port."</span><br><span>@@ -257,4 +258,11 @@</span><br><span> </span><br><span> endchoice</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config FSP_PARAM_OVERRIDE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Use This should be selected if the SoC and the mainboard implement</span><br><span style="color: hsl(120, 100%, 40%);">+ function callbacks to populate/override the FSP UPD parameters.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 065d92b..761fe81 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -37,6 +37,7 @@</span><br><span> ramstage-y += chip.c</span><br><span> ramstage-y += cpu.c</span><br><span> ramstage-y += finalize.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += graphics.c</span><br><span> ramstage-y += gspi.c</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 30719ed..0c0a05d 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -95,43 +95,6 @@</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void parse_devicetree(FSP_S_CONFIG *params)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(0, 100%, 40%);">- if (!dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Could not find root device\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- const config_t *config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">- const int SerialIoDev[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_I2C0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_I2C1,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_I2C2,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_I2C3,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_I2C4,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_I2C5,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_GSPI0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_GSPI1,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_GSPI2,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_UART0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_UART1,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_UART2</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_slot(0, SerialIoDev[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!dev->enabled) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->SerialIoDevMode[i] = PchSerialIoDisabled;</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- params->SerialIoDevMode[i] = PchSerialIoPci;</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->SerialIoDevMode[i] == PchSerialIoAcpi ||</span><br><span style="color: hsl(0, 100%, 40%);">- config->SerialIoDevMode[i] == PchSerialIoHidden)</span><br><span style="color: hsl(0, 100%, 40%);">- params->SerialIoDevMode[i] = config->SerialIoDevMode[i];</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void soc_init_pre_device(void *chip_info)</span><br><span> {</span><br><span> /* Perform silicon specific init. */</span><br><span>@@ -177,139 +140,3 @@</span><br><span> .enable_dev = &soc_enable,</span><br><span> .init = &soc_init_pre_device,</span><br><span> };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* UPD parameters to be initialized before SiliconInit */</span><br><span style="color: hsl(0, 100%, 40%);">-void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_S_CONFIG *params = &supd->FspsConfig;</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(0, 100%, 40%);">- config_t *config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Parse device tree and enable/disable devices */</span><br><span style="color: hsl(0, 100%, 40%);">- parse_devicetree(params);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Load VBT before devicetree-specific config. */</span><br><span style="color: hsl(0, 100%, 40%);">- params->GraphicsConfigPtr = (uintptr_t)vbt_get();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set USB OC pin to 0 first */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb2OverCurrentPin[i] = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb3OverCurrentPin[i] = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_silicon_init_params(params);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Unlock upper 8 bytes of RTC RAM */</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchLockDownRtcMemoryLock = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SATA */</span><br><span style="color: hsl(0, 100%, 40%);">- params->SataEnable = config->SataEnable;</span><br><span style="color: hsl(0, 100%, 40%);">- params->SataMode = config->SataMode;</span><br><span style="color: hsl(0, 100%, 40%);">- params->SataSalpSupport = config->SataSalpSupport;</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(params->SataPortsEnable, config->SataPortsEnable,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(params->SataPortsEnable));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(params->SataPortsDevSlp));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Lan */</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchLanEnable = config->PchLanEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Audio */</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaDspEnable = config->PchHdaDspEnable;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* S0ix */</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchPmSlpS0Enable = config->s0ix_enable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* USB */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->PortUsb20Enable[i] =</span><br><span style="color: hsl(0, 100%, 40%);">- config->usb2_ports[i].enable;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb2OverCurrentPin[i] =</span><br><span style="color: hsl(0, 100%, 40%);">- config->usb2_ports[i].ocpin;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb2AfePetxiset[i] =</span><br><span style="color: hsl(0, 100%, 40%);">- config->usb2_ports[i].pre_emp_bias;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb2AfeTxiset[i] =</span><br><span style="color: hsl(0, 100%, 40%);">- config->usb2_ports[i].tx_bias;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb2AfePredeemp[i] =</span><br><span style="color: hsl(0, 100%, 40%);">- config->usb2_ports[i].tx_emp_enable;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb2AfePehalfbit[i] =</span><br><span style="color: hsl(0, 100%, 40%);">- config->usb2_ports[i].pre_emp_bit;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->PortUsb30Enable[i] = config->usb3_ports[i].enable;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->usb3_ports[i].tx_de_emp) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb3HsioTxDeEmphEnable[i] = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb3HsioTxDeEmph[i] =</span><br><span style="color: hsl(0, 100%, 40%);">- config->usb3_ports[i].tx_de_emp;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->usb3_ports[i].tx_downscale_amp) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb3HsioTxDownscaleAmpEnable[i] = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Usb3HsioTxDownscaleAmp[i] =</span><br><span style="color: hsl(0, 100%, 40%);">- config->usb3_ports[i].tx_downscale_amp;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable xDCI controller if enabled in devicetree and allowed */</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_slot(0, PCH_DEVFN_USBOTG);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!xdci_can_enable())</span><br><span style="color: hsl(0, 100%, 40%);">- dev->enabled = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- params->XdciEnable = dev->enabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PCI Express */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->PcieClkSrcUsage[i] == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(config->PcieClkSrcUsage));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(config->PcieClkSrcClkReq));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* eMMC and SD */</span><br><span style="color: hsl(0, 100%, 40%);">- params->ScsEmmcEnabled = config->ScsEmmcEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->EmmcHs400DllNeed == 1) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchScsEmmcHs400RxStrobeDll1 =</span><br><span style="color: hsl(0, 100%, 40%);">- config->EmmcHs400RxStrobeDll1;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- params->ScsSdCardEnabled = config->ScsSdCardEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->ScsUfsEnabled = config->ScsUfsEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- params->Heci3Enabled = config->Heci3Enabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->Device4Enable = config->Device4Enable;</span><br><span style="color: hsl(0, 100%, 40%);">- params->SkipMpInit = !chip_get_fsp_mp_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* VrConfig Settings for 5 domains</span><br><span style="color: hsl(0, 100%, 40%);">- * 0 = System Agent, 1 = IA Core, 2 = Ring,</span><br><span style="color: hsl(0, 100%, 40%);">- * 3 = GT unsliced, 4 = GT sliced */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)</span><br><span style="color: hsl(0, 100%, 40%);">- fill_vr_domain_config(params, i, &config->domain_vr_config[i]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Vt-D config */</span><br><span style="color: hsl(0, 100%, 40%);">- tconfig->VtdDisable = config->VtdDisable;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Mainboard GPIO Configuration */</span><br><span style="color: hsl(0, 100%, 40%);">-__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c</span><br><span>new file mode 100644</span><br><span>index 0000000..4b983d6</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/fsp_params.c</span><br><span>@@ -0,0 +1,200 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/xdci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/vbt.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void parse_devicetree(FSP_S_CONFIG *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Could not find root device\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ const int SerialIoDev[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_I2C0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_I2C1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_I2C2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_I2C3,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_I2C4,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_I2C5,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_GSPI0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_GSPI1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_GSPI2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_UART0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_UART1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_DEVFN_UART2</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, SerialIoDev[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev->enabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SerialIoDevMode[i] = PchSerialIoDisabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SerialIoDevMode[i] = PchSerialIoPci;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->SerialIoDevMode[i] == PchSerialIoAcpi ||</span><br><span style="color: hsl(120, 100%, 40%);">+ config->SerialIoDevMode[i] == PchSerialIoHidden)</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SerialIoDevMode[i] = config->SerialIoDevMode[i];</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* UPD parameters to be initialized before SiliconInit */</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_CONFIG *params = &supd->FspsConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Parse device tree and enable/disable devices */</span><br><span style="color: hsl(120, 100%, 40%);">+ parse_devicetree(params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Load VBT before devicetree-specific config. */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->GraphicsConfigPtr = (uintptr_t)vbt_get();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set USB OC pin to 0 first */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb2OverCurrentPin[i] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb3OverCurrentPin[i] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_silicon_init_params(params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Unlock upper 8 bytes of RTC RAM */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchLockDownRtcMemoryLock = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SataEnable = config->SataEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SataMode = config->SataMode;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SataSalpSupport = config->SataSalpSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(params->SataPortsEnable, config->SataPortsEnable,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(params->SataPortsEnable));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(params->SataPortsDevSlp));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lan */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchLanEnable = config->PchLanEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaDspEnable = config->PchHdaDspEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* S0ix */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchPmSlpS0Enable = config->s0ix_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PortUsb20Enable[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->usb2_ports[i].enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb2OverCurrentPin[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->usb2_ports[i].ocpin;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb2AfePetxiset[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->usb2_ports[i].pre_emp_bias;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb2AfeTxiset[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->usb2_ports[i].tx_bias;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb2AfePredeemp[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->usb2_ports[i].tx_emp_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb2AfePehalfbit[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->usb2_ports[i].pre_emp_bit;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PortUsb30Enable[i] = config->usb3_ports[i].enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->usb3_ports[i].tx_de_emp) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb3HsioTxDeEmphEnable[i] = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb3HsioTxDeEmph[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->usb3_ports[i].tx_de_emp;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->usb3_ports[i].tx_downscale_amp) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb3HsioTxDownscaleAmpEnable[i] = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Usb3HsioTxDownscaleAmp[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->usb3_ports[i].tx_downscale_amp;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable xDCI controller if enabled in devicetree and allowed */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!xdci_can_enable())</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->enabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->XdciEnable = dev->enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Express */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->PcieClkSrcUsage[i] == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(config->PcieClkSrcUsage));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(config->PcieClkSrcClkReq));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* eMMC and SD */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsEmmcEnabled = config->ScsEmmcEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->EmmcHs400DllNeed == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchScsEmmcHs400RxStrobeDll1 =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->EmmcHs400RxStrobeDll1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsSdCardEnabled = config->ScsSdCardEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsUfsEnabled = config->ScsUfsEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Heci3Enabled = config->Heci3Enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->Device4Enable = config->Device4Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SkipMpInit = !chip_get_fsp_mp_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* VrConfig Settings for 5 domains</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = System Agent, 1 = IA Core, 2 = Ring,</span><br><span style="color: hsl(120, 100%, 40%);">+ * 3 = GT unsliced, 4 = GT sliced */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_vr_domain_config(params, i, &config->domain_vr_config[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Vt-D config */</span><br><span style="color: hsl(120, 100%, 40%);">+ tconfig->VtdDisable = config->VtdDisable;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Mainboard GPIO Configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h</span><br><span>index 9ea60ae..6faf110 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/romstage.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/romstage.h</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #define _SOC_ROMSTAGE_H_</span><br><span> </span><br><span> #include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span> #include <fsp/api.h></span><br><span> </span><br><span> void mainboard_memory_init_params(FSPM_UPD *mupd);</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc</span><br><span>index 99bc25f..ab3e8e2 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc</span><br><span>@@ -15,4 +15,5 @@</span><br><span> </span><br><span> romstage-y += power_state.c</span><br><span> romstage-y += romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c</span><br><span> romstage-y += systemagent.c</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>new file mode 100644</span><br><span>index 0000000..67aa0ec</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>@@ -0,0 +1,74 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mask = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set IGD stolen size to 64MB. */</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->IgdDvmt50PreAlloc = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->IedSize = CONFIG_IED_REGION_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->SaGv = config->SaGv;</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->UserBd = BOARD_TYPE_ULT_ULX;</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->RMT = config->RMT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->PcieRpEnable[i])</span><br><span style="color: hsl(120, 100%, 40%);">+ mask |= (1 << i);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->PcieRpEnableMask = mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->PrmrrSize = config->PrmrrSize;</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->EnableC6Dram = config->enable_c6dram;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable Cpu Ratio Override temporary. */</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->CpuRatio = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable Vmx if Vt-d is already disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->VtdDisable)</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->VmxEnable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->VmxEnable = config->VmxEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(dev != NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_memory_init_params(m_cfg, config);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable SMBus controller based on config */</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->SmbusEnable = config->SmbusEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set debug probe type */</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->PlatformDebugConsent = config->DebugConsent;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_memory_init_params(mupd);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Do nothing */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>index ae1ba4d..113798d 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>@@ -146,55 +146,3 @@</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int i;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mask = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set IGD stolen size to 64MB. */</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->IgdDvmt50PreAlloc = 2;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->IedSize = CONFIG_IED_REGION_SIZE;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->SaGv = config->SaGv;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->UserBd = BOARD_TYPE_ULT_ULX;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->RMT = config->RMT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->PcieRpEnable[i])</span><br><span style="color: hsl(0, 100%, 40%);">- mask |= (1 << i);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->PcieRpEnableMask = mask;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->PrmrrSize = config->PrmrrSize;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->EnableC6Dram = config->enable_c6dram;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable Cpu Ratio Override temporary. */</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->CpuRatio = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable Vmx if Vt-d is already disabled */</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->VtdDisable)</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->VmxEnable = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->VmxEnable = config->VmxEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);</span><br><span style="color: hsl(0, 100%, 40%);">- assert(dev != NULL);</span><br><span style="color: hsl(0, 100%, 40%);">- const config_t *config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- soc_memory_init_params(m_cfg, config);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable SMBus controller based on config */</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->SmbusEnable = config->SmbusEnable;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set debug probe type */</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->PlatformDebugConsent = config->DebugConsent;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_memory_init_params(mupd);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__weak void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Do nothing */</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28661">change 28661</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28661"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e </div>
<div style="display:none"> Gerrit-Change-Number: 28661 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>